updated verilog SDRAM controller.
disabled serial audio, enabled new SDRAM controller.
updated files list.
sdram_ctrl cleanup.
moved rtl/de1 to rtl/clock, updated project files with new paths for clock & sdram modules.
fixed a typo, cleanup.
removed old tg68 core.
sdram_ctrl code simplified, cleanup.
extended instruction cache, very little gain (1%).
updated sim environment.
fixed a typo for simulation code.
some temporary changes for sdram.
testing version of cache.
added 7MHz clock enable on 28MHz clock domain.
changed clock port name for Amber.
cleaned-up & re-arranged.
added mist documentation.
updated file permissions.
added mist fpga project files.
project file for mist board updated.