msm: board-8960: Modify SMPS7 min, max voltage limits for 8960ab

PM8921 SMPS7 is the parent regulator for the LDOs which supply
to the Q6 processors. The worst case voltage for Q6 processor
on 8960ab is 1.075V (compared to 1.05V on 8960). Raise the S7
voltage constraints from 1.15V to 1.275V in order to accommodate
the increase in Q6 supply voltage.

CRs-Fixed: 507062
Change-Id: If3e249b6412d141d7108332b43481e127c350bb2
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Bluetooth: Handle transaction collision for set_encryption command.

Found with some IOT devices, the set_encryption command from DUT
can collide with remote device command to do role switch. In this
case DUT and remote device should handle the collision properly
without disconnection to have proper interoperability. The current
change is to re-issue host command to start_encryption when the
failure from the remote device is Transaction collision.

Change-Id: I4c883378385f7c1bc55b6c3c5507ad68ec7e8581
CRs-Fixed: 519730
Signed-off-by: Gubbala Venugopal Rao <vgubba@codeaurora.org>
Merge "msm: board-8960: Modify SMPS7 min, max voltage limits for 8960ab"
Merge "Bluetooth: Handle transaction collision for set_encryption command."
wcnss: Do not log CCPU registers

Accessing CCPU registers during WDI timeout can cause timeout issues
when common_ss is power collapsed. So remove the CCPU register dump from
reset intrrupt API.

Change-Id: I4945d827c1840e85e796c276c45f7cf23cbe2b2a
CRs-Fixed: 517940
Signed-off-by: Sameer Thalappil <sameert@codeaurora.org>
Merge "wcnss: Do not log CCPU registers"
msm: spm: modify power collapse seq for kraitv3

High sleep current observed due to L2 cache not going into
power collapse in special cases.

While analyzing, a timing issue was found that can manifest itself when the
clamp signal is asserted during the Krait CPU1 power collapse sequence.
When it occurs, the issue causes an L2 FIFO to falsely believe that it
has data to return to CPU1 when it does not.The condition isnt detected until
later when CPU0 and the L2 attempt to collapse.

This condition keeps the L2 from going idle which keeps it from power
collapsing after both CPUs have collapsed.  This in turn prevents the
RPM from enabling a system low power state (VDD minimization).
The issue is likely process/temp/voltage dependent.

HW team recommended a workaround, the details are as below.

Add commands to the Krait CPU power collapse SPM sequences to assert
Krait CPU reset prior to asserting the CPU clamp signal and de-assert
CPU reset after the CPU clamp is asserted.
Since the CPU clocks are gated (by the first SPM command in the
sequence), and the clamp is applied, the Krait CPU will do nothing
when its reset is de-asserted.

The workaround involves changing both CPU power collapse SPM sequences
(Power Collapse with and without RPM notification).

CRs-fixed: 518750
Change-Id: I62c76f49a96a8cb6ecf67733ae9a7ff1a79a76f7
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Merge "msm: spm: modify power collapse seq for kraitv3"