Synthesised ENoC as a simple Single Cycle MESH.

• Added a file, synthesis_wrap, so that when synthesising the inputs and
outputs of the network were not assigned to I/O pins on an FPGA.

• Had to change generate loops, gave them names and removed genvar out
of the definition of the loop.  This was so that Quartus would compile
the code.

• Had problems compiling functions.sv - kept claiming multiple instances
- so stopped using it and just declared my own log2 function in the top
module.

• Lots of other minor errors picked up during synthesis were corrected

• Changed VirtualChannel to VOQ to more accurately represent what the
module does.