de0_nano: add build verilator
de0_nano: changes for build with verilator
de0_nano: build with verilator is working. ADD: Generic main RAM, new wb_arbiter(wb_arbiter_men) to join acess of ram (instructions and data) PROBLEMS: sdram memory controller,  SPI, clockgeneration module, Altera vitual Jtag tap
de0_nano: verialtor working with systemc, without Jtag now SIM and UART0
deo_nano: missing file,systems/de0_nano/bench/verilator
missing file
de0_nano: add necessary files for define jtag now SIM
verilator working in systemC  without uart
de0_nano: systemC is working  in  verilator,with jtag and uart. but or1200 dont send addr for uart, wb_intercon.v: It is possible the UART addr is incorrect
Merge branch 'de0_systemC'
branch de0_systemC
Merge remote-tracking branch 'jose/master'
merge
jtag define
merged
Merge branch 'master' of https://github.com/Carlosaarodrigues/orpsoc-cores