i965: Change signature of brw_get_depthstencil_tile_masks

Add two new parameters, 'level' and 'layer'. A later patch will pass the
new parameters to intel_miptree_slice_has_hiz().

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
i965: Fix typo in doxygen hyperlink

s/brw_state_upload/brw_upload_state/

Found because the link was broken.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
intel: Replace checks for hiz_mt with has_hiz accessors

That is, replace checks like `hiz_mt != NULL` with
`intel_miptree_slice_has_hiz(...)` where appropriate. This is necessary
because a later patch will selectively disable hiz on individual miptree
slices, and therefore `hiz_mt != NULL` will no longer be a valid
indicator.

This produces no behaviorial change because currently, when a hiz miptree
is present, hiz is enabled for all slices in the tree.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
WIP/intel: Disable hiz on individual miptree slices

TODO: 3d textures
TODO: doc
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
WIP/intel: Add padding to depth and hiz miptrees

TODO: doc
WIP/i965/blorp: Align vertices for hiz ops
intel: Enable hiz on Haswell

This patch sets the flag. That's all.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>