Update libtool to support Android.

* m4/libtool.m4: Add "linux*android*" case.  Taken from the libtool
repository.
--

The patch, which cleanly applies, is

  commit 8eeeb00daef8c4f720c9b79a0cdb89225d9909b6
  Author: David 'Digit' Turner <digit@google.com>
  Date:   Tue Oct 8 14:37:32 2013 -0700

  This patch adds proper Android support to libtool. The main
  issues are the following:

      - Versioned libraries are not supported by the platform and
        its build/packaging tools.

      - The dynamic linker is not GNU ld, there is no support for
        DT_RUNPATH.

      - Similarly, there is no ldconfig.

Signed-off-by: Werner Koch <wk@gnupg.org>
Fix one-off memory leak when build with Linux capability support.

* src/secmem.c (lock_pool, secmem_init): Use cap_free.  Reported by
Mike Crowe <mac@mcrowe.com>.

Signed-off-by: Werner Koch <wk@gnupg.org>
Fix last commit (9a37470c)

* src/secmem.c (lock_pool): Remove remaining line.  Reported by Ian
Goldberg.
random: Add a feature to close device file descriptors.

* src/gcrypt.h.in (GCRYCTL_CLOSE_RANDOM_DEVICE): New.
* src/global.c (_gcry_vcontrol): Call _gcry_random_close_fds.
* random/random.c (_gcry_random_close_fds): New.
* random/random-csprng.c (_gcry_rngcsprng_close_fds): New.
* random/random-fips.c (_gcry_rngfips_close_fds): New.
* random/random-system.c (_gcry_rngsystem_close_fds): New.
* random/rndlinux.c (open_device): Add arg retry.
(_gcry_rndlinux_gather_random): Add mode to close open fds.

* tests/random.c (check_close_random_device): New.
(main): Call new test.

Signed-off-by: Werner Koch <wk@gnupg.org>
Remove macro hacks for internal vs. external functions.  Part 2 and last.

* src/visibility.h: Remove remaining define/undef hacks for symbol
visibility.  Add macros to detect the use of the public functions.
Change all affected functions by replacing them by the x-macros.
* src/g10lib.h: Add internal prototypes.
(xtrymalloc, xtrycalloc, xtrymalloc_secure, xtrycalloc_secure)
(xtryrealloc, xtrystrdup, xmalloc, xcalloc, xmalloc_secure)
(xcalloc_secure, xrealloc, xstrdup, xfree): New macros.

--

The use of xmalloc/xtrymalloc/xfree is a more common pattern than the
gcry_free etc. functions.  Those functions behave like those defined
by C and thus for better readability we  use these macros and not
the underscore prefixed functions.

Signed-off-by: Werner Koch <wk@gnupg.org>
Move list of hardware features to hwfeatures.c.

* src/global.c (hwflist, disabled_hw_features): Move to ..
* src/hwfeatures.c: here.
(_gcry_disable_hw_feature): New.
(_gcry_enum_hw_features): New.
(_gcry_detect_hw_features): Remove arg DISABLED_FEATURES.
* src/global.c (print_config, _gcry_vcontrol, global_init): Adjust
accordingly.
--

It is better to keep the hardware feature infor at one place.

Signed-off-by: Werner Koch <wk@gnupg.org>
Add a configuration file to disable hardware features.

* src/hwfeatures.c: Inclyde syslog.h and ctype.h.
(HWF_DENY_FILE): New.
(my_isascii): New.
(parse_hwf_deny_file): New.
(_gcry_detect_hw_features): Call it.

* src/mpicalc.c (main): Correctly initialize Libgcrypt.  Add options
"--print-config" and "--disable-hwf".

Signed-off-by: Werner Koch <wk@gnupg.org>
SHA-256: Add SSSE3 implementation for x86-64

* cipher/Makefile.am: Add 'sha256-ssse3-amd64.S'.
* cipher/sha256-ssse3-amd64.S: New.
* cipher/sha256.c (USE_SSSE3): New.
(SHA256_CONTEXT) [USE_SSSE3]: Add 'use_ssse3'.
(sha256_init, sha224_init) [USE_SSSE3]: Initialize 'use_ssse3'.
(transform): Rename to...
(_transform): This.
[USE_SSSE3] (_gcry_sha256_transform_amd64_ssse3): New.
(transform): New.
* configure.ac (HAVE_INTEL_SYNTAX_PLATFORM_AS): New check.
(sha256): Add 'sha256-ssse3-amd64.lo'.
* doc/gcrypt.texi: Document 'intel-ssse3'.
* src/g10lib.h (HWF_INTEL_SSSE3): New.
* src/hwfeatures.c (hwflist): Add "intel-ssse3".
* src/hwf-x86.c (detect_x86_gnuc): Test for SSSE3.
--

Patch adds fast SSSE3 implementation of SHA-256 by Intel Corporation. The
assembly source is licensed under 3-clause BSD license, thus compatible
with LGPL2.1+. Original source can be accessed at:
 http://www.intel.com/p/en_US/embedded/hwsw/technology/packet-processing#docs

Implementation is described in white paper
 "Fast SHA - 256 Implementations on Intel® Architecture Processors"
 http://www.intel.com/content/www/us/en/intelligent-systems/intel-technology/sha-256-implementations-paper.html

Benchmarks:

cpu                 Old         New         Diff
Intel i5-4570       13.99 c/B   10.66 c/B   1.31x
Intel i5-2450M      21.53 c/B   15.79 c/B   1.36x
Intel Core2 T8100   20.84 c/B   15.07 c/B   1.38x

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
SHA-512: Add SSSE3 implementation for x86-64

* cipher/Makefile.am: Add 'sha512-ssse3-amd64.S'.
* cipher/sha512-ssse3-amd64.S: New.
* cipher/sha512.c (USE_SSSE3): New.
(SHA512_CONTEXT) [USE_SSSE3]: Add 'use_ssse3'.
(sha512_init, sha384_init) [USE_SSSE3]: Initialize 'use_ssse3'.
[USE_SSSE3] (_gcry_sha512_transform_amd64_ssse3): New.
(transform) [USE_SSSE3]: Call SSSE3 implementation.
* configure.ac (sha512): Add 'sha512-ssse3-amd64.lo'.
--

Patch adds fast SSSE3 implementation of SHA-512 by Intel Corporation. The
assembly source is licensed under 3-clause BSD license, thus compatible
with LGPL2.1+. Original source can be accessed at:
 http://www.intel.com/p/en_US/embedded/hwsw/technology/packet-processing#docs

Implementation is described in white paper
 "Fast SHA512 Implementations on Intel® Architecture Processors"
 http://www.intel.com/content/www/us/en/intelligent-systems/intel-technology/fast-sha512-implementations-ia-processors-paper.html

Benchmarks:

cpu                 Old         New         Diff
Intel i5-4570       10.11 c/B    7.56 c/B   1.33x
Intel i5-2450M      14.11 c/B   10.53 c/B   1.33x
Intel Core2 T8100   11.92 c/B   10.22 c/B   1.16x

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
SHA-512: Add AVX and AVX2 implementations for x86-64

* cipher/Makefile.am: Add 'sha512-avx-amd64.S' and
'sha512-avx2-bmi2-amd64.S'.
* cipher/sha512-avx-amd64.S: New.
* cipher/sha512-avx2-bmi2-amd64.S: New.
* cipher/sha512.c (USE_AVX, USE_AVX2): New.
(SHA512_CONTEXT) [USE_AVX]: Add 'use_avx'.
(SHA512_CONTEXT) [USE_AVX2]: Add 'use_avx2'.
(sha512_init, sha384_init) [USE_AVX]: Initialize 'use_avx'.
(sha512_init, sha384_init) [USE_AVX2]: Initialize 'use_avx2'.
[USE_AVX] (_gcry_sha512_transform_amd64_avx): New.
[USE_AVX2] (_gcry_sha512_transform_amd64_avx2): New.
(transform) [USE_AVX2]: Add call for AVX2 implementation.
(transform) [USE_AVX]: Add call for AVX implementation.
* configure.ac (HAVE_GCC_INLINE_ASM_BMI2): New check.
(sha512): Add 'sha512-avx-amd64.lo' and 'sha512-avx2-bmi2-amd64.lo'.
* doc/gcrypt.texi: Document 'intel-cpu' and 'intel-bmi2'.
* src/g10lib.h (HWF_INTEL_CPU, HWF_INTEL_BMI2): New.
* src/hwfeatures.c (hwflist): Add "intel-cpu" and "intel-bmi2".
* src/hwf-x86.c (detect_x86_gnuc): Check for HWF_INTEL_CPU and
HWF_INTEL_BMI2.
--

Patch adds fast AVX and AVX2 implementation of SHA-512 by Intel Corporation.
The assembly source is licensed under 3-clause BSD license, thus compatible
with LGPL2.1+. Original source can be accessed at:
 http://www.intel.com/p/en_US/embedded/hwsw/technology/packet-processing#docs

Implementation is described in white paper
 "Fast SHA512 Implementations on Intel® Architecture Processors"
 http://www.intel.com/content/www/us/en/intelligent-systems/intel-technology/fast-sha512-implementat$

Note: AVX implementation uses SHLD instruction to emulate RORQ, since it's
      faster on Intel Sandy-Bridge. However, on non-Intel CPUs SHLD is much
      slower than RORQ, so therefore AVX implementation is (for now) limited
      to Intel CPUs.
Note: AVX2 implementation also uses BMI2 instruction rorx, thus additional
      HWF flag.

Benchmarks:

cpu                 Old         SSSE3       AVX/AVX2   Old vs AVX/AVX2
                                                              vs SSSE3
Intel i5-4570       10.11 c/B    7.56 c/B   6.72 c/B   1.50x  1.12x
Intel i5-2450M      14.11 c/B   10.53 c/B   8.88 c/B   1.58x  1.18x

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
Fix W32 build

* random/rndw32.c (register_poll, slow_gatherer): Change gcry_xmalloc to
xmalloc, and gcry_xrealloc to xrealloc.
--

Patch fixes following errors:

../random/.libs/librandom.a(rndw32.o): In function `registry_poll':
.../libgcrypt/random/rndw32.c:434: undefined reference to `__gcry_USE_THE_UNDERSCORED_FUNCTION'
.../libgcrypt/random/rndw32.c:454: undefined reference to `__gcry_USE_THE_UNDERSCORED_FUNCTION'
../random/.libs/librandom.a(rndw32.o): In function `slow_gatherer':
.../random/rndw32.c:658: undefined reference to `__gcry_USE_THE_UNDERSCORED_FUNCTION'

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
Fix empty clobber in AVX2 assembly check

* configure.ac (gcry_cv_gcc_inline_asm_avx2): Add "cc" as assembly
globber.
--

Appearently empty globbers only work in some cases on linux, and fail on
mingw32.

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
doc: Minor manual fix.

--
Update license information

* LICENSES: New.
* Makefile.am (EXTRA_DIST): Add LICENSES.
* AUTHORS: Add list of copyright holders.
* README: Reference AUTHORS.

Signed-off-by: Werner Koch <wk@gnupg.org>
Add missing register clearing in to SHA-256 and SHA-512 assembly

* cipher/sha256-ssse3-amd64.S: Clear used XMM/YMM registers at return.
* cipher/sha512-avx-amd64.S: Ditto.
* cipher/sha512-avx2-bmi2-amd64.S: Ditto.
* cipher/sha512-ssse3-amd64.S: Ditto.
--

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
SHA-1: Add SSSE3 implementation

* cipher/Makefile.am: Add 'sha1-ssse3-amd64.c'.
* cipher/sha1-ssse3-amd64.c: New.
* cipher/sha1.c (USE_SSSE3): New.
(SHA1_CONTEXT) [USE_SSSE3]: Add 'use_ssse3'.
(sha1_init) [USE_SSSE3]: Initialize 'use_ssse3'.
(transform): Rename to...
(_transform): this.
(transform): New.
* configure.ac [host=x86_64]: Add 'sha1-ssse3-amd64.lo'.
--

Patch adds SSSE3 implementation based on white paper "Improving the Performance
of the Secure Hash Algorithm (SHA-1)" at
 http://software.intel.com/en-us/articles/improving-the-performance-of-the-secure-hash-algorithm-1

Benchmarks:

cpu                Old        New        Diff
Intel i5-4570      9.02 c/B   5.22 c/B   1.72x
Intel i5-2450M     12.27 c/B  7.24 c/B   1.69x
Intel Core2 T8100  7.94 c/B   6.76 c/B   1.17x

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
Convert SHA-1 SSSE3 implementation from mixed asm&C to pure asm

* cipher/Makefile.am: Change 'sha1-ssse3-amd64.c' to
'sha1-ssse3-amd64.S'.
* cipher/sha1-ssse3-amd64.c: Remove.
* cipher/sha1-ssse3-amd64.S: New.
--

Mixed C&asm implementation appears to trigger GCC bugs easily. Therefore
convert SSSE3 implementation to pure assembly for safety.

Benchmark also show smallish speed improvement.

cpu             C&asm     asm
Intel i5-4570   5.22 c/B  5.09 c/B
Intel i5-2450M  7.24 c/B  7.00 c/B

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
SHA-1/SSSE3: Do not check for Intel syntax assembly support

* cipher/sha1-ssse3-amd64.S: Remove check for
HAVE_INTEL_SYNTAX_PLATFORM_AS.
* cipher/sha1.c [USE_SSSE3]: Ditto.
--

SHA-1 SSSE3 implementation uses AT&T syntax so check for
HAVE_INTEL_SYNTAX_PLATFORM_AS is unnecessary.

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
Minor fixes to SHA assembly implementations

* cipher/Makefile.am: Correct 'sha256-avx*.S' to 'sha512-avx*.S'.
* cipher/sha1-ssse3-amd64.S: First line, correct filename.
* cipher/sha256-ssse3-amd64.S: Return correct stack burn depth.
* cipher/sha512-avx-amd64.S: Use 'vzeroall' to clear registers.
* cipher/sha512-avx2-bmi2-amd64.S: Ditto and return correct stack burn
depth.
--

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
tests: Prevent rare failure of gcry_pk_decrypt test.

* tests/basic.c (check_pubkey_crypt): Add special mode 1.
(main): Add option --loop.

--

This failure has been reported by Jussi Kivilinna.  The new loop
option was needed to track that down.  It took me up to 100 iterations
to trigger the bug.  With the fix applied I am currently at 1000
iteration with no problems.  Command line to evoke the problem was:

  ./basic --pubkey --verbose --loop -1 --die

Signed-off-by: Werner Koch <wk@gnupg.org>