Fix set_spr functions

These needed to be Verilog tasks and to write to both register files.
mor1kx-defines: add defines for OR1k 1.0 compatibility

Define VR2 field to be 3 bytes, {major, minor, pipeline ID}

Set version to 0.1

Define numbers for each pipeline ID
mor1kx-sprs: bring up to date with OR1K 1.0
mor1kx_cfgrs: bring up to date with OR1K 1.0

Add UVRP to VR
Add VR2
Add new bits to CPUCFGR
mor1kx_ctrl_cappuccino: update for OR1K 1.0

Add ISRs, update instantiation of mor1kx_cfgrs
mor1kx_ctrl_espresso: update for OR1K 1.0

Add ISRs, update instantiation of mor1kx_cfgrs
mor1kx_ctrl_prontoespresso: update for OR1K 1.0

Add ISRs, update instantiation of mor1kx_cfgrs
Remove remains from when icache was located outside cpu
cappuccino/ctrl_branch: connect pipeline_flush to imm_branch reset
move dcache to lsu
(pronto)espresso/cpu: remove ic/dc spr signals

icache and dcache are internal units now
cappuccino/lsu: connect execute lsu address

and rename signals to their respective pipeline stage
cappuccino: fix a bug related to syscall exception

if a l.sys instruction would be followed by a branch,
the branch target of the branch would be taken instead of the
exception vector of the syscall.
pic: ack all spr accesses, not only writes
ticktimer: ack all spr accesses, not only writes
execute_alu: add support for overflow, carry and divide by zero

Add support for the add-with-carry-in instruction.

Generate carry (unsigned overflow) for add, addc, sub, mulu and divide by zero for divu.

Generate overflow (signed overflow) for add, addc, sub, mul and divide by zero for div.
espresso: add carry and overflow support
pronto espresso: add carry and overflow support
cappuccino: add carry, overflow and range exception support
espresso: update get_gpr