msm: smsm: Rename LTE Coexistence Bit

The LTE Coexistence bit has been renamed to just SMSM_PROC_AWAKE since
it is now being used for more general is-processor-awake signaling.

Change-Id: I9007c6c91ce3338c790864bf09318edbcb6d50c0
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
msm: smsm: Add processor AWAKE signaling

This processor-awake signaling can be used by remote processors to
determine if the Apps processor is asleep and if so, if it wants to send
data to the Apps processor that would trigger a wakeup sequence.

Change-Id: I4db5891023956b27a91afc2712f9ca053f9648e5
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
msm: display: Clear performance request data in turning on

In resume, previous cached request data needs be cleared as
they do not reflect the current hw status.

Signed-off-by: Ken Zhang <kenz@codeaurora.org>
msm: iommu: Synchronize access to IOMMU cfg port

Add remote spinlock that allows CPU and GPU to
synchronize access to IOMMU hardware.

Add usage of remote spinlock to iommu driver and
add depenency on SFPB hardware mutex being enabled.`

This feature is not using SFPB hardware mutex. However,
SFPB hardware mutex must be enabled since the remote
spinlock implementation is making use of shared memory
that is normally used when SFPB hardware mutex is not enabled.

Change-Id: I42e11d742e295110843c4b45d6d27cc665d42b7b
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Alex Wong <waiw@codeaurora.org>
msm: Kconfig: Enable IOMMU CPU-GPU synchronization

Enable synchronization between CPU and GPU for
IOMMU configuration register accesses.

Change-Id: I7409090c0fc811fa28562644bcbfd4f91a8a7425
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>

Conflicts:

	arch/arm/mach-msm/Kconfig
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
Signed-off-by: Alex Wong <waiw@codeaurora.org>
msm: kgsl: Synchronize access to IOMMU cfg port

Add a software based spinlock between CPU and GPU.
This spinlock is used to grant mutually exclusive access to
SMMU configuration between CPU and GPU. This mutual exclusion
is required to prevent deadlock in the system.
CRs-Fixed: 409198
Change-Id: Ic375beaaf4c5505b41d3fabc4adf15965d71b13a
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Alex Wong <waiw@codeaurora.org>
msm: kgsl: Idle GPU core before programming SMMU from CPU

Always idle the GPU core before programming SMMU from CPU for
SMMU-v1. GPU core was already being idled before programming
the pagetable register, make sure that it's also idle before
programming the tlb invalidate registers. This is required to
prevent a deadlock from happening at the bus level.

Change-Id: Ie901b92028b289fc546ab6186eedd01411d0727e
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
Signed-off-by: Alex Wong <waiw@codeaurora.org>
msm_fb: display: update var in display commit

Need the value of var in display commit to update the double buffers.
If not, double buffering doesn't work in minui (eg. recovery and off-charger
mode)

Change-Id: I1fba52243cc781f18742131759245911d32c9b18
msm: display: Fix blend configuration for video layer with MDP composition

With video layer in MDP composition, there is no need to apply destination
over blend rule, as z-order of layers take care of proper staging of layers
by default. Apply constant blend to the video layer when in MDP composition

CRs-fixed: 437965
Change-Id: I7476659f12cdf06018bf6ace829a836c86ae97e8
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>