New Predication test bench programs

Simplest A-port/B-port only, and AB-both I/O pass-throughs,
and a set of periodically stalled accumulators.

Notably: the pipelined IO_ready makes for an unexpected
starting state for all the threads, as some are stalled
until the real IO_ready signal catches up.
Bugfix: had the PC calculations using IO_ready wrong.

Hopefully, this code synthesizes well, and doesn't introduce a critical path.
Next step: complete test harness and verify under Quartus.