ashmem: fix deadlock when system is low on memory
RTC: twl6030: correct usage of static register while reading RTC

RTC: twl6030: correct usage of static register while reading RTC

RTC stores time and date in several registers. Due to the fact that
these registers can't be read momentary there is a chance that reading
from counting registers gives an error of one minute, one hour,
one day, etc. To address the issue the RTC has hardware that can copy
the counting registers to static shadowed registers. However, while
re-using driver code for twl6030, the feature wasn't correctly
implemented. So wrong time was read one - two times per 300000 readings.
This patch corrects usage of RTC registers for twl6030.

Change-Id: Iab1a9afd381e2a3de3b6b381ebf9bb8b798a6e18
Signed-off-by: Konstantin Shlyakhovoy <x0155534@ti.com>
ARM: OMAP4: l2x0: Set optimized value for prefetch offset
ARM: OMAP4: l2x0: Set optimized value for prefetch offset

Tuning the value of prefetch offset register of PL310 cache controller
for OMAP4 family. The patch can give up to 4% better results in low level
benchmarks (like bw_mem at block size above 2 Mb) and up to 2% in benchmarks
imitating use cases (like Sunspider).
Note: if double line fill is enabled, the optimal value can be different.
Revert "ARM: OMAP4: l2x0: Set optimized value for prefetch offset"

This reverts commit f067adc45ba082d19ef8a0bb3c2caef090e8fe63.
ARM: OMAP4: l2x0: Cleanup prefetch offset register setting

ARM: OMAP4: l2x0: Cleanup prefetch offset register setting

The bits [31:5] of Prefetch Offset Register are reserved in
PL310 r2p0 so they should be kept unchanged.
It's enough to set Data prefetch enable bit in PL310 auxiliary
control register to enable the feature, so setting of bit 28 of POR
is removed.
Before writing POR value, the bits [4:0] has to be cleared to remove
previous value.

Change-Id: Id5d047da0daa0c841c69d4d587d2280d2f3433f9
Signed-off-by: Konstantin Shlyakhovoy <x0155534@ti.com>
ARM: OMAP4: l2x0: Set optimized value for prefetch offset
ARM: OMAP4: l2x0: Set optimized value for prefetch offset

Tuning the value of prefetch offset register of PL310 cache controller
for OMAP4 family. The patch can give up to 4% better results in low level
benchmarks (like bw_mem at block size above 2 Mb) and up to 2% in benchmarks
imitating use cases (like Sunspider).
Note: if double line fill is enabled, the optimal value can be different.
Reduced Android Logger RAM usage. TNX to sakindia123@xda for point.
cpufreq: freed stats table caused memory leak