delay blocks removed and latency given to convert blocks
35x25 bit DSP48E multiplier; this block might have strange simulation
problems
instantiate control using dsp48e_ctrl block generator function
cleanup to mult_35x25 blocks. Still getting strange errors (e.g. seems
like reinterpret blocks after DSP slices are required to prevent cleanup
errors..)
used 'reinterp_uint' block generator
couple more blocks simplified
all blocks after dsp converted
removed comments
cleaned up var names
only slices and dsps remaining
slices after DSP replaced with slice_off_bottom function
var renaming
generic slice partitioning function used; all blocks except DSP blocks
replaced
final reorg and commenting; test still passes!
testbench for mult_35x25 added
vacc extended to 2^2 inputs (problems with bram latency being too short)
modified to propagate input to output, to allow inline insertion of
block without requiring additonal wiring
changes (additions) to reinterpret/concatenate block generators after
mult_35x25 debugging
hack-fixed Xilinx inconsistency with string datatypes (string for 2's
comp datatype occasionally has extra spaces, but only for some
blocks....)
init commit of a generic DSP48E accumulator (not vector accumulator!).
lots of features to add