hdl/ip_cores/: add dsp-cores submodule
wb_fmc516/wbgen/*: (1/3) add regular delay control register
wb_fmc516/wbgen/*: (2/3) add regular delay control register
emb-sw/*fmc516*: add regular delay control support
hdl/*: update Manifest files
wb_fmc516/wbgen/*: (3/3) add regular delay control register
Merge branch 'wb-fmc516-devel' into dsp-devel
Merge branch 'emb-sw-devel' into dsp-devel
hdl/platform/*: add new chipscope ILA
hdl/top/dbe_bpm_dsp/*: add dsp top files
hdl/syn/dbe_bpm_dsp/*: add dsp syn top files
hdl/syn/loader/*: change bitstream file
emb-sw/*: add delay to specific channels and enable ADC data input
hdl/*/wb_fmc516/*: simpler valid data generation

Also, only generic fifos from general-cores are used.
No more coregen stuff here
emb-sw/*: update fmc516 register definition
hdl/ip_cores/dsp-cores/: update submodule reference
hdl/*/wb_fmc516/*: (1/4) clearer register names and sanitization
hdl/*/wb_fmc516/*: (2/4) clearer register names and sanitization
hdl/*/wb_fmc516/*: (3/4) clearer register names and sanitization
hdl/*/wb_fmc516/*: (4/4) clearer register names and sanitization