Tentatively set Gerber output options in board file.
Renamed layers to make layer order explicit on Gerber output.
Don't use aux origin for Gerbers, drill file.
Don't subtract mask from silk, let PCB vendor do that.
Knitted an island of V1P8 near the clock generator to the image plane going to the FPGA (and supply).
Added V1P8 knitting between planes at the DDR2 socket (near where the supply lives).