arc: add "invalidate_dcache_all"

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
arc: make "invalidate_icache_all" similar to D$.

In case of IVIC *any* write triggers invalidation we may use the same
value (1) as for D$ which requres LSB bit to be set for invalidation.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
xplorer: fix cache line length (32 bytes instead of 64)

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
arc: don't invalidate I$ if it is disabled

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
net/designware: make driver compatible with data cache

Up until now this driver only worked with data cache disabled.
To make it work with enabled data cache following changes were required:

 * Implement all accesses to shared structures between CPU and GMAC via
uncached reads/writes ("readl"/"writel").
 * Flush cache for data passed from CPU to GMAC
 * Invalidate cache for data passed from GMAC to CPU
 
I tried to implement items above keeping as much code unchanged as
possible. So logic of operation is kept as it is.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>