InstCombine: (icmp eq B, 0) | (icmp ult A, B) -> (icmp ule A, B-1)

This transform allows us to turn IR that looks like:
  %1 = icmp eq i64 %b, 0
  %2 = icmp ult i64 %a, %b
  %3 = or i1 %1, %2
  ret i1 %3

into:
  %0 = add i64 %b, -1
  %1 = icmp uge i64 %0, %a
  ret i1 %1

which means we go from lowering:
        cmpq    %rsi, %rdi
        setb    %cl
        testq   %rsi, %rsi
        sete    %al
        orb     %cl, %al
        ret

to lowering:
        decq    %rsi
        cmpq    %rdi, %rsi
        setae   %al
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185677 91177308-0d34-0410-b5e6-96231b3b80d8
Add a --crash option to not.

Now the two possible uses of not are
* not cmd
  Will return true if cmd doesn't crash and returns false.
* not --crash cmd
  Will return true if cmd crashes.

It will be used/tested in a followup commit for the clang crash recovery
testing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185678 91177308-0d34-0410-b5e6-96231b3b80d8
Use the raw member names in Archive::Archive.

This a bit more efficient and avoids having a function that uses the string
table being called by a function that searches for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185680 91177308-0d34-0410-b5e6-96231b3b80d8
Don't treat bitcode files specially in llvm-ar.

We really want bitcode files to behave as regular object files in archives, so
we don't need to track that a member is bitcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185681 91177308-0d34-0410-b5e6-96231b3b80d8
PR16490: fix a crash in ARMDAGToDAGISel::SelectInlineAsm.

In the SelectionDAG immediate operands to inline asm are constructed as
two separate operands. The first is a constant of value InlineAsm::Kind_Imm
and the second is a constant with the value of the immediate.

In ARMDAGToDAGISel::SelectInlineAsm, if we reach an operand of Kind_Imm we
should skip over the next operand too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185688 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify code. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185689 91177308-0d34-0410-b5e6-96231b3b80d8
Remove NoOperation.

parseCommandLine prints and error and exists if no operation is specified, so
it never returns NoOperation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185691 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] Support @tls in the asm parser

This adds support for the last missing construct to parse TLS-related
assembler code:
   add 3, 4, symbol@tls

The ADD8TLS currently hard-codes the @tls into the assembler string.
This cannot be handled by the asm parser, since @tls is parsed as
a symbol variant.  This patch changes ADD8TLS to have the @tls suffix
printed as symbol variant on output too, which allows us to remove
the isCodeGenOnly marker from ADD8TLS.  This in turn means that we
can add a AsmOperand to accept @tls marked symbols on input.

As a side effect, this means that the fixup_ppc_tlsreg fixup type
is no longer necessary and can be merged into fixup_ppc_nofixup.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185692 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] Make test case buildable with GNU as

The ppc64-fixups.s test currently fails to build with GNU as, since it
does not support plain symbols as arguments to li/lis.  Rewrite the test
for R_PPC64_ADDR16 and R_PPC64_REL16 to use lwz instead.

Allowing the test case to be built with both LLVM and GNU as makes it
easier to spot unwanted difference in the output.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185694 91177308-0d34-0410-b5e6-96231b3b80d8
Use simpler version of exists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185695 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Clean up register scavenging code

SystemZ wants normal register scavenging slots, as close to the stack or
frame pointer as possible.  The only reason it was using custom code was
because PrologEpilogInserter assumed an x86-like layout, where the frame
pointer is at the opposite end of the frame from the stack pointer.
This meant that when frame pointer elimination was disabled,
the slots ended up being as close as possible to the incoming
stack pointer, which is the opposite of what we want on SystemZ.

This patch adds a new knob to say which layout is used and converts
SystemZ to use target-independent scavenging slots.  It's one of the pieces
needed to support frame-to-frame MVCs, where two slots might be required.

The ABI requires us to allocate 160 bytes for calls, so one approach
would be to use that area as temporary spill space instead.  It would need
some surgery to make sure that the slot isn't live across a call though.

I stuck to the "isFPCloseToIncomingSP - ..." style comment on the
"do what the surrounding code does" principle.  The FP case is already
covered by several Systemz/frame-* tests, which fail without the
PrologueEpilogueInserter change, so no new ones are needed.

No behavioural change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185696 91177308-0d34-0410-b5e6-96231b3b80d8
Don't create an archive if, for example, we are asked to print the index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185697 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Allocate a second register scavenging slot

This is another prerequisite for frame-to-frame MVC copies.
I'll commit the patch that makes use of the slot separately.

The downside of trying to test many corner cases with each of the
available addressing modes is that a fair few tests need to account
for the new frame layout.  I do still think it's useful to have all
these tests though, since it's something that wouldn't get much coverage
otherwise.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185698 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] Add some special @got@tprel fixup cases

When a target@got@tprel or target@got@tprel@l symbol variant is used in
a fixup_ppc_half16 (*not* fixup_ppc_half16ds) context, we currently fail,
since the corresponding R_PPC64_GOT_TPREL16 / R_PPC64_GOT_TPREL16_LO
relocation types do not exist.

However, since such symbol variants resolve to GOT offsets which are
always 4-aligned, we can simply instead use the _DS variants of the
relocation types, which *do* exist.

The same applies for the @got@dtprel variants.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185700 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Enable the use of MVC for frame-to-frame spills

...now that the problem that prompted the restriction has been fixed.

The original spill-02.py was a compromise because at the time I couldn't
find an example that actually failed without the two scavenging slots.
The version included here did.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185701 91177308-0d34-0410-b5e6-96231b3b80d8
Fix double renaming bug in stack coloring pass

The stack coloring pass renumbered frame indexes with a loop of the form:

  for each frame index FI
    for each instruction I that uses FI
      for each use of FI in I
        rename FI to FI'

This caused problems if an instruction used two frame indexes F0 and F1
and if F0 was renamed to F1 and F1 to F2.  The first time we visited the
instruction we changed F0 to F1, then we changed both F1s to F2.

In other words, the problem was that SSRefs recorded which instructions
used an FI, but not which MachineOperands and MachineMemOperands within
that instruction used it.

This is easily fixed for MachineOperands by walking the instructions
once and processing each operand in turn.  There's already a loop to
do that for dead store elimination, so it seemed more efficient to
fuse the two at the block level.

MachineMemOperands are more tricky because they can be shared between
instructions.  The patch handles them by making SSRefs an array of
MachineMemOperands rather than an array of MachineInstrs.  We might end
up processing the same MachineMemOperand twice, but that's OK because
we always know from the SSRefs index what the original frame index was.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185703 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Remove redundant frame MMOs

This fixes foldMemoryOperandImpl() so that it doesn't create duplicated
frame MMOs.  I hadn't realized when writing r185434 that it was the caller's
responsibility to add these.

No behavioural change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185704 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Remove no-op MVCs

The stack coloring pass has code to delete stores and loads that become
trivially dead after coloring.  Extend it to cope with single instructions
that copy from one frame index to another.

The testcase happens to show an example of this kicking in at the moment.
It did occur in Real Code too though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185705 91177308-0d34-0410-b5e6-96231b3b80d8
Remove a useless declarations (found by scan-build)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185709 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: Fix incorrect pack pattern

A "pkhtb x, x, y asr #num" uses the lower 16 bits of "y asr #num" and packs them
in the bottom half of "x". An arithmetic and logic shift are only equivalent in
this context if the shift amount is 16. We would be shifting in ones into the
bottom 16bits instead of zeros if "y" is negative.

radar://14338767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185712 91177308-0d34-0410-b5e6-96231b3b80d8