Change RX sampling time to happen in the middle of the bit

Hi,

I used your project as starting point for implementing an UART module. While investigating it I found that the RX sampling happens very early inside a bit, see the commited before.png
This isn't very robust and could cause troube with faulty data sampling.
Therefore I changed the code to sample in the middle of the bit, as you can see in after.png

The change is rather large because I detected the issue during my rework of reducing the logic usage for CPLD, by removing the double sampling clock generation counters.
And I also added "Optimize Here" Markers for later trials - please ignore them for now.

Just let me know if something is unclear.

You can find my testbench and project setup here in case you're interested:
https://github.com/sd2k9/hdl_uart_echo