Adding multiple module support for MCJIT.

Tests to follow.

PIC with small code model and  EH frame handling will not work with multiple modules.  There are also some rough edges to be smoothed out for remote target support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191722 91177308-0d34-0410-b5e6-96231b3b80d8
Tests for MCJIT multiple module support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191723 91177308-0d34-0410-b5e6-96231b3b80d8
SelectionDAG: Clarify comments from r191600

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191724 91177308-0d34-0410-b5e6-96231b3b80d8
BEXTR should be defined to take same type for bother operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191728 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unneeded fields from disassembler internal instruction format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191731 91177308-0d34-0410-b5e6-96231b3b80d8
Remove 0 as a valid encoding for the m-mmmm field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191732 91177308-0d34-0410-b5e6-96231b3b80d8
AVX-512: Added X86vzmovl patterns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191733 91177308-0d34-0410-b5e6-96231b3b80d8
This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191734 91177308-0d34-0410-b5e6-96231b3b80d8
Fix pattern sort in DAGISelEmitter.cpp

The old code skipped one of the sorting criteria if either pattern had
no types.  This could lead to cycles of the form X < Y, Y < Z, Z < X.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191735 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191737 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Reapply: Add definitions of LFH and STFH

Originally committed as r191661, but reverted because it changed the matching
order of comparisons on some hosts.  That should have been fixed by r191735.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191738 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Use upper words of GR64s for codegen

This just adds the basics necessary for allocating the upper words to
virtual registers (move, load and store).  The move support is parameterised
in a way that makes it easy to handle zero extensions, but the associated
zero-extend patterns are added by a later patch.

The easiest way of testing this seemed to be add a new "h" register
constraint for high words.  I don't expect the constraint to be useful
in real inline asms, but it should work, so I didn't try to hide it
behind an option.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191739 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Add sign-extending high-word loads (LBH and LHH)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191740 91177308-0d34-0410-b5e6-96231b3b80d8
SCEVExpander: Fix a regression I introduced by to eagerly adding RAII objects.

PR17425.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191741 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Add zero-extending high-word loads (LLCH and LLHH)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191742 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Add truncating high-word stores (STCH and STHH)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191743 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM] Introduce the 'sevl' instruction in ARMv8.

This also removes the restriction on the immediate field of the 'hint'
instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8
Remove empty directory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191745 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Add register zero extensions involving at least one high word


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191746 91177308-0d34-0410-b5e6-96231b3b80d8
Test commit. Updated comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191748 91177308-0d34-0410-b5e6-96231b3b80d8