mor1kx-defines: add defines for OR1k 1.0 compatibility

Define VR2 field to be 3 bytes, {major, minor, pipeline ID}

Set version to 0.1

Define numbers for each pipeline ID
mor1kx-sprs: bring up to date with OR1K 1.0
mor1kx_cfgrs: bring up to date with OR1K 1.0

Add UVRP to VR
Add VR2
Add new bits to CPUCFGR
mor1kx_ctrl_cappuccino: update for OR1K 1.0

Add ISRs, update instantiation of mor1kx_cfgrs
mor1kx_ctrl_espresso: update for OR1K 1.0

Add ISRs, update instantiation of mor1kx_cfgrs
mor1kx_ctrl_prontoespresso: update for OR1K 1.0

Add ISRs, update instantiation of mor1kx_cfgrs
Remove remains from when icache was located outside cpu
cappuccino/ctrl_branch: connect pipeline_flush to imm_branch reset
move dcache to lsu
(pronto)espresso/cpu: remove ic/dc spr signals

icache and dcache are internal units now
cappuccino/lsu: connect execute lsu address

and rename signals to their respective pipeline stage
cappuccino: fix a bug related to syscall exception

if a l.sys instruction would be followed by a branch,
the branch target of the branch would be taken instead of the
exception vector of the syscall.
Add dmmu implementation

A first rough draft, a lot of cleaning is still needed,
but it pass the DMMU part of the or1200-dmmu test.