Add some delays to sync and scope_ctrl

This will hopefully make these high fan-out signals easier to route.
Update fft_core to mlib_devel 369c12c, HDL adders

This ensures that all delays in fft_core use behavioral HDL (i.e. have
"reg_retiming" set to "on").

Additionally, the 'DSP48s adders in butterfly' checkbox has been UNchecked (so
now it will use behavioral HDL for the butterfly adders) and the "Add Latency"
has been changed from 2 to 4.
Update fft_core netlist

Built using mlib_devel version 369c12c.
Tweak fft_core.mdl, update to mlib_devel c3a5dc3

Update fft_core to mlib_devel c3a5dc3.
Change adder latency from 4 to 3.
Change delays-in-bram threshold from 2^8 to 2^6.
Change twiddles-in-bram threshold from 2^8 to 2^6.
Tweak fft_core.mdl, update to mlib_devel 576a59b

Update fft_core to mlib_devel 576a59b.
Disable "Store a fraction of coeff factors where useful" option
Disable "Generate coeffs with multipliers where useful" option
Update fft_core netlist

Built using mlib_devel version 576a59b.
Add sma_corr_2013_Oct_30_1349.bof

Built using mlib_devel 576a59b.  This build actually failed timing by 3 ps on
two paths, but a BOF file was created anyway with the expectation that 3 ps
"over all temperatures is *nothing*" (famous last words).
Ran resynth_netlist on fft_core netlist
Ran resynth_netlist on fft_core netlist

Added -opt_mode=area and -glob_opt-=allclocknets to the default resynth_netlist
options:

resynth_netlist('fft_core', ...
  '-opt_mode','area', ...
  '-glob_opt','allclocknets', ...
  '-register_balancing','yes', ...
  '-optimize_primitives','yes', ...
  '-read_cores','yes')
Add sma_corr_2013_Oct_31_1323.bof

Built using mlib_devel 576a59b.  This build met timing at 143 MHz fabric clock.