Fixing a 64-bit conversion warning in MSVC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182018 91177308-0d34-0410-b5e6-96231b3b80d8
Add more addFrameMove test coverage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182019 91177308-0d34-0410-b5e6-96231b3b80d8
Use new CHECK-DAG support to stabilize CodeGen/PowerPC/recipest.ll

While testing some experimental code to add vector-scalar registers to
PowerPC, I noticed that a couple of independent instructions were
flipped by the scheduler.  The new CHECK-DAG support is perfect for
avoiding this problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182020 91177308-0d34-0410-b5e6-96231b3b80d8
More addFrameMove test coverage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182021 91177308-0d34-0410-b5e6-96231b3b80d8
Add a triple to the test to try to fix the windows bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182022 91177308-0d34-0410-b5e6-96231b3b80d8
PPC32 cannot form counter loops around i64 FP conversions

On PPC32, i64 FP conversions are implemented using runtime calls (which clobber
the counter register). These must be excluded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182023 91177308-0d34-0410-b5e6-96231b3b80d8