[translate and mem_opb_attach] adjusts translate code to skip addresses by 8

According to the MIG documentation and the ddr3_controller code,
the MIG is set up with BL8 encoding (Burst Length 8) where word
length is 72, so a burst of 8 is in fact 288*2 bits.  The address
should skip by 8 every time, so that for a given address 2 288 bit
words are retrieved from the ddr3, each on a separate clock cycle.
This has been tested and cuts the errors in half relative
to the mistaken skip by 4 addressing.  Errors now occur on 0.03%
of reads, but the errors can be large as they are either 0 or
have a few bits flipped.
[opbaddr_2_Dnum_O9num.v] maps all 9 32-bit words from ddr3 288 bit word, and maps the rest of the space to 0

this maps between the opb virtual address space and the ddr3 address space

BL8 encoding is used in the MIG, so for a given ddr3 address, 8 72-bit
words are produced as 2 288-bit words (denoted here as DXa and DXb where X
is the ddr3 address value given to the controller, skips by 8.) These
two words are produced on consecutive ddr3 clock cycles.

Unfortunately, in a 288 bit word there are 9 32-bit words, or 9 opb-sized
words.  example: opb read from opb address space 17 will produce data
from the second 288 bit ddr3 word produced from ddr3 address 0, and from that
word we will map to chunk 1 (starting from 0) indicating a slice of bits 32:63.
I am arbitrarily saying that opb address 17 then maps to D0b-O1. "D" indicates
ddr3 sized words (288) and O indicates opb-sized words (32).  The first
48 consecutive reads from opb space are shown below:

0      1      2      3      4      5      6      7      8      9  10  11  12  13  14  15
D0a-O0 D0a-O1 D0a-O2 D0a-O3 D0a-O4 D0a-O5 D0a-O6 D0a-O7 D0a-O8 0  0   0   0   0   0   0

16     17     18     19     20     21     22     23     24     25 26  27  28  29  30  31
D0b-O0 D0b-O1 D0b-O2 D0b-O3 D0b-O4 D0b-O5 D0b-O6 D0b-O7 D0b-O8 0  0   0   0   0   0   0

32     33     34     35     36     37     38     39     40     41 42  43  44  45  46  47
D8a-O0 D8a-O1 D8a-O2 D8a-O3 D8a-O4 D8a-O5 D8a-O6 D8a-O7 D8a-O8 0  0   0   0   0   0   0

with some opb virtual memory locations mapped to 0 arbitrarily.
can still implement a divide by 9, but this is ok for now. All of this
map shown above would be produced from executing a read from ddr3
address 0 as given to the ddr3 controller.  The next ddr3 address
given to the controller will be 8, and the code developed here
accounts for that.

In terms of opb virtual memory space, only 2^16 bytes are allocated.
So given that roughly half are mapped to 0, this lets us read 2^15 bytes of
data, or roughly 32 kB.  To access all 4 GB of data from the ddr3
address, the "software_address_bits" are used to designate which 2^16 byte
chunk of data to which the opb address space is currently mapped.