target-arm: add secure/normal world banks for CP15 TLS registers
target-arm: add CP15 VBAR and MVBAR registers to vmstate.
target-arm: add secure/normal world banks for CP15 FCSE registers.
target-arm: fix CPREG_IS_SECURE macro
target-arm: add secure/normal world banks of SCTLR register
target-arm: Prepare emulation of TrustZone normal/secure world MMU support.

This patch adds the core support infrastructure required to emulate
the secure and normal world MMU views of a TrustZone system. This patch
comprises the following (atomically) related changes:

* Introduce two additional ARM MMU modes for use by the normal world
  kernel/user-mode simulation.

* Add secure/normal world banks of MMU related CP15 registers.
  (TTBCR, TTBR0/1, IFAR, DFAR, DFSR, IFSR, PA)

  Note that the banked nature of these registers only applies to
  systems with an MMU (VMSA). Microcontrollers with an MPU (PMSAv5)
  only use the "secure" half of the banked c5_data/c5_insn registers
  to encode their memory access permissions.

* Adapt the MMU translation logic in get_phys_addr() to honor the
  security state of the processor core. A new "is_secure" parameter
  selects the CP15 register bank to be used for translation. Support
  for the VMSAv6/v7 "NS" bit in section translations will be added
  in a later patch of this series.

  The mmu_idx parameter is used in cpu_arm_handle_mmu_fault() to
  determine the world causing an MMU fault. Debug access in
  cpu_get_phys_page_debug() uses the arm_current_secure() function to
  determine the current world for translating MMU requests.

Note that this patch does not wire-up the new normal world MMU modes
in translate.c, in order to isolate infrastructure changes from binary
translator changes. The existing binary translator is compatible with
this patch for secure-world only guests.