MIPS: use inline directive for __in*s functions

All other IO accessor functions are using the
'inline' directive. Use that also for the __in*s
to make it consistent with the other variants.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: convert IO port accessor functions to 'static inline'

The currently used 'extern inline' directive causes
the following compiler warnings if CONFIG_SWAP_IO_SPACE
is defined:

  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outlc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outl_p' which is not static [enabled by default]
  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outlc' which is not static [enabled by default]
  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outl' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outwc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outw_p' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outwc' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outw' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inlc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inl_p' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inlc' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inl' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inwc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inw_p' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inwc' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inw' which is not static [enabled by default]

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: start{, 64}.S: fill branch delay slots with NOP instructions

The romReserved and romExcHandle handlers are
accessed by a branch instruction however the
delay slots of those instructions are not filled.

Because the start.S uses the 'noreorder' directive,
the assembler will not fill the delay slots either,
and leads to the following assembly code:

  0000056c <romReserved>:
   56c:   1000ffff        b       56c <romReserved>

  00000570 <romExcHandle>:
   570:   1000ffff        b       570 <romExcHandle>

In the resulting code, the second branch instruction
is placed into the delay slot of the first branch
instruction, which is not allowed on the MIPS
architecture.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: start.S: fix boundary check in relocate_code

The loop code copies more data with one than
necessary due to the 'ble' instuction. Use the
'blt' instruction instead to fix that.

Due to the lack of suitable hardware the Xburst
specific code is compile tested only. However the
change is quite obvious.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: start.S: set sp register directly

The current code uses two instructions to load
the stack pointer into the 'sp' register.

This results in the following assembly code:

    468:   3c088040        lui     t0,0x8040
    46c:   251d0000        addiu   sp,t0,0

The first instuction loads the stack pointer into
the 't0' register then the value of the 'sp' register
is computed by adding zero to the value of the 't0'
register. The same issue present on the 64-bit version
as well:

    56c:   3c0c8040        lui     t0,0x8040
    570:   659d0000        daddiu  sp,t0,0

Change the code to load the stack pointer directly
into the 'sp' register. The generated code is functionally
equivalent to the previous version but it is simpler.

  32-bit:
    468:   3c1d8040        lui     sp,0x8040

  64-bit:
    56c:   3c1d8040        lui     sp,0x8040

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: start.S: save reused arguments earlier in relocate_code

Save the reused parameters at the beginning
of the 'relocate_code' function. This makes
the function a bit more readable.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: start.S: simplify relocation offset calculation

The current code uses four instructions and a
temporary register to calculate the relocation
offset and to adjust the gp register.

The relocation offset can be calculated directly
from the CONFIG_SYS_MONITOR_BASE constant and from
the destination address. The resulting offset can
be used to adjust the gp pointer.

This approach makes the code a bit simpler because
it needs two instructions only.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: start.S: don't save flush_cache parameters in advance

Saving the parameters in advance unnecessarily complicates
the code. The destination address is already saved in the
's2' register, and that register is not clobbered by the
copy loop. The size of the copied data can be computed
after the copy loop is done.

Change the code to compute the size parameter right
before calling flush_cache, and set the destination
address parameter in the delay slot of the actuall
call.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
powerpc/p2041: move Lanes mux to board early init

Lanes mux currently is configured in eth.c when initializing FMAN ethernet
ports, but SRIO and PCIe also need lanes mux, so we move the lanes mux to
p2041rdb.c which implements a board-specific initialization and will be
called at early stage.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/t4qds: move VSC3316 config data from t4qds.h to t4qds.c

Static variables should be defined in C files, not header files, because
otherwise every C file that #includes the header file will generate a
duplicate of the variables.  Since the vsc3316_xxx[] arrays are only
used by t4qds.c anyway, just put the variables there.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/mpc85xx: Reserve default boot page

The boot page in memory is already reserved so OS won't overwrite.
As long as the boot page translation is active, the default boot page
also needs to be reserved in case the memory is 4GB or more.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
board/T4240qds:Fix TLB and LAW size of NAND flash

The internal SRAM of Freescale's IFC NAND machine is of 64K and controller's
Address Mask Registers is initialised with the same.

So Update TLB and LAW size of NAND flash accordingly.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
boards/T4240qds:Fix IFC AMASK init as per FPGA register space

T4240QDS's QIXIS FPGA has 4k register space size and IFC controller's
Address Mask Registers is initialised 64K size.

So Fix the Address Mask Register initilisation as 4K

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/t4240qds: Update IFC timing for NOR flash

Relax parameters to give address latching more time to setup.
Tighten parameters to make it overall faster.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/mpc8572ds: Enable bank interleaving to cs0+cs1 for dual-rank DIMMs

The controller interleaving only takes the usable memory mapped to cs0. In
the case of bank interleaving not enabled, only half of dual-rank DIMM will
be used.

For single-rank DIMM bank interleaving will be auto disabled.

Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/mpc8544ds: Add USB controller support for MPC8544DS

USB controller in uboot is a required feature for MPC8544DS. Without this
support there is no 'usb' command in uboot.

Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/mpc85xx: Few updates for B4860 cpu changes

- Added some more serdes1 and serdes2 combinations
  serdes1= 0x2c, 0x2d, 0x2e
  serdes2= 0x7a, 0x8d, 0x98
- Updated Number of DDR controllers to 2.
- Added FMAN file for B4860, drivers/net/fm/b4860.c

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/mpc85xx:Add support of B4420 SoC

B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900
and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and
reduced target frequencies.

Key differences between B4860 and B4420
----------------------------------------
B4420 has:
1. Fewer e6500 cores: 1 cluster with 2 e6500 cores
2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
3. Single DDRC
4. 2X 4 lane serdes
5. 3 SGMII interfaces
6. no sRIO
7. no 10G

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
board/freescale/common:Add support of QTAG register

QIXIS FPGA's QIXIS Tag Access register (QTAG) defines TAG, VER, DATE, IMAGE
fields. These fields have FPGA build version, image name and build date
information.

Add support to parse these fields to have complete FPGA image information.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/mpc85xx:Fix Core cluster configuration loop

Different personalities/derivatives of SoC may have reduced cluster. But it is
not necessary for last valid DCFG_CCSR_TP_CLUSTER register to have
DCFG_CCSR_TP_CLUSTER[EOC] bit set to represent "End of Clusters".

EOC bit can still be set in last DCFG_CCSR_TP_CLUSTER register of orignal SoC
which may not be valid for the personality.
So add initiator type check to find valid cluster.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>