ARM: tegra: enterprise: Add A03/A04 support

Bug 939799

Reviewed-on: http://git-master/r/90824
(cherry-picked from commit 8c556f816196c17e059db2c11b966ca89848efa3)

Change-Id: I67b26958862b8b60217c2750fe0b2eef3013d9b3
Signed-off-by: Tom Cherry <tcherry@nvidia.com>
Reviewed-on: http://git-master/r/92409
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
tty: serial: core: Fix console resume for PORT_TEGRA

WAR to enable console prints when console service is not started
for port type TEGRA.

Bug 958959

Change-Id: I51e582d16195171f1f8bae9324e2ddece4638281
Signed-off-by: Pradeep Kumar <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/92814
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Joshua Cha <joshuac@nvidia.com>
Tested-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
arm: tegra: emc scaling for enterprise

Need to include A01 board for emc scaling.

Bug 957981

Reviewed-on: http://git-master/r/91877
(cherry picked from commit 2dff127a133056b4229b8d7a4e8328959873f3c8)

Change-Id: I9c615b13adf4375ee0742b817361b0d6326afccd
Signed-off-by: Tom Cherry <tcherry@nvidia.com>
Reviewed-on: http://git-master/r/93050
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
arm: tegra: enterprise: use proper backlight clk_div for A03/A04

The new TPS61160A part asks for the control PWM signal to be between
5kHZ and 100kHz.  This change sets clk_div to 0x1D for a 5kHz signal.

This change also installs a linear table for
enterprise_bl_output_measured_a03.

Bug 956246

Reviewed-on: http://git-master/r/91606
(cherry picked from commit 32a67cf7b1c8223abe8de7d88b4bcd1906cda0a2)

Change-Id: Ic7907cfae6f918ef055add33615822ef8c5e0ec6
Signed-off-by: Tom Cherry <tcherry@nvidia.com>
Reviewed-on: http://git-master/r/93051
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
tegra: p1852: correcting the GPIO to use for therm_alert

Currently the GPIO that we are trying to use for therm_alert is
GPIO_PW2 which is incorrect. The GPIO we ought to use is GPIO_PW3.

Bug 920368.

(cherry picked from commit ad4714c486c6a734681287ea4d85869f05704397)
Change-Id: If1a8cf4b8cdbdd69f2d01f4c292775d413384bc0
Reviewed-on: http://git-master/r/#change,74273
Signed-off-by: Vishal Singh <vissingh@nvidia.com>
Reviewed-on: http://git-master/r/91730
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
i2c: tegra: Avoid duplicate write into Tx fifo

Dvc I2C_DONE_INTR_EN interrupt bit is always enable into dvc
control register3. During normal transaction on dvc i2c bus
sometimes one transaction written two times in TX fifo buffer
because of triggered dvc interrupt. This is causing to corrupt
the next transaction header and send wrong address over dvc
i2c bus. To solve this issue dvc i2c interrupt has to disable
during filling of Tx fifo and enable after that.

Updated the following things in code:
(1) Add the code to mask/unmask I2C_DONE_INTR_EN into dvc control reg3
writing into Tx Fifo register.
(2) Put delay before resetting the controller

Hand-picked this change from: http://git-master/r/#change,39997
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>

Change-Id: I16b5821e1d0d0cf8419ce9d239e794de9d5b47be
Reviewed-on: http://git-master/r/89456
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
i2c: tegra: Fix to avoid possible race condition

Because of race condition between isr and tx fifo fill,
duplicate data is being written. So added locking to make
Tx fifo fill as atomic.

Change-Id: Ia99466adadfb6d86a6f238ec4cd0aa13bd36e434
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/90870
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
tegra: p1852: Register tegra WDT platform device

bug 924362

Change-Id: I878a845d5c78b2f8c0f5882f8c0a97b3842ac883
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/91224
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
tegra: hdmi: Add 1080p timing table

Bug 949759

Add new 1080p timing support, or 1080p playback is not available on
some monitors like Acer H243HX

Change-Id: I8a8a3a5b2de71d5a56dad233f953e09176f85b76
Signed-off-by: Hao Tang <htang@nvidia.com>
Reviewed-on: http://git-master/r/91732
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
mfd: max8907c: Do not use I2C_M_NOSTART in first message

It is not recommended to use the flag I2C_M_NOSTART in first
message.

The documentation kernel/Documentation/i2c/i2c-proocol says:
Flag I2C_M_NOSTART:
    In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some
    point. For example, setting I2C_M_NOSTART on the second partial message
    generates something like:
      S Addr Rd [A] [Data] NA Data [A] P
    If you set the I2C_M_NOSTART variable for the first partial message,
    we do not generate Addr, but we do generate the startbit S. This will
    probably confuse all other clients on your bus, so don't try this.

Change-Id: I8a8a4f6f91a1b53b6d443588ab18704cf100fd50
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/93187
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Bandi Krishna Chaitanya <bandik@nvidia.com>
dmaengine: move last completed cookie into generic dma_chan structure

Every DMA engine implementation declares a last completed dma cookie
in their private dma channel structures.  This is pointless, and
forces driver specific code.  Move this out into the common dma_chan
structure.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
[imx-sdma.c & mxs-dma.c]
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
cherry-picked from mainline
		4d4e58de32a192fea65ab84509d17d199bd291c8

Change-Id: Ib653bcfa5f492986946fd34006a8de3090db0441
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/93778
dmaengine: add private header file

Add a local private header file to contain definitions and declarations
which should only be used by DMA engine drivers.

We also fix linux/dmaengine.h to use LINUX_DMAENGINE_H to guard against
multiple inclusion.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
[imx-sdma.c & mxs-dma.c]
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
(cherry picked from mainline commit d2ebfb335b0426deb1a4fb14e4e926d81ecd8235)

Change-Id: I91b051537fa1890e2651ebe0409fa97cbc9191dd
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/93779
Reviewed-by: Automatic_Commit_Validation_User
dmaengine: consolidate assignment of DMA cookies

Everyone deals with assigning DMA cookies in the same way (it's part of
the API so they should be), so lets consolidate the common code into a
helper function to avoid this duplication.

Change-Id: I730882ff0f84f9ae42dd137a8926b7ae10868370
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
[imx-sdma.c & mxs-dma.c]
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
(cherry picked from mainline commit 884485e1f12dcd39390f042e772cdbefc9ebb750)

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: Ifc4a395a5dbafad03f8b28e052ad0e7ea5d90163
Reviewed-on: http://git-master/r/93780
Reviewed-by: Automatic_Commit_Validation_User
dmaengine: provide a common function for completing a dma descriptor

Provide a common function to do the cookie mechanics for completing
a DMA descriptor.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
[imx-sdma.c & mxs-dma.c]
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
Cherry-picked from mainline commit
	f7fbce07c6ce26a25b4e0cb5f241c361fde87901

Change-Id: I0b0a9d4ad538db4fda227cc91436c44bc4a6f206
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/93781
Reviewed-by: Automatic_Commit_Validation_User
dmaengine: consolidate tx_status functions

Now that we have the completed cookie in the dma_chan structure, we
can consolidate the tx_status functions by providing a function to set
the txstate structure and returning the DMA status.  We also provide
a separate helper to set the residue for cookies which are still in
progress.

Change-Id: I4b7672bbd17d072bfde348d04481c8db48e814c4
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
[imx-sdma.c & mxs-dma.c]
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
(cherry picked from mainline commit
	96a2af41c78b1fbb1f567a3486bdc63f7b31c5fd)

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: Ifdb55d85eb4789f221679f1f38f5566168e5c643
Reviewed-on: http://git-master/r/93782
Reviewed-by: Automatic_Commit_Validation_User
dmaengine: consolidate initialization of cookies

Provide a common function to initialize a channels cookie values.

Change-Id: Idc822d69971d7a6d26ffea8809df4825b87020e5
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
[imx-sdma.c & mxs-dma.c]
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
(cherry picked from mainline commit
	d3ee98cdcd6198ea1cf75c603178acc8a805b69b)

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: Id7d52f05b78d15b0c61cb04122b19810e78b9269
Reviewed-on: http://git-master/r/93783
dmaengine/dw_dmac: Reconfigure interrupt and chan_cfg register on resume

In S2R all DMA registers are reset by hardware and thus they are required to be
reprogrammed. The channels which aren't reprogrammed are channel configuration
and interrupt enable registers, which are currently programmed at chan_alloc
time.

This patch creates another routine to initialize a channel. It will try to
initialize channel on every dwc_dostart() call. If channel is already
initialised then it simply returns, otherwise it configures registers.

This routine will also initialize registers on wakeup from S2R, as we mark
channels as uninitialized on suspend.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
cherry-picked from mainline 61e183f8306934a9f66557f69f1f0f56f18dca06

Change-Id: I4ede3e1db8844533161bd4a836b1fece0d0ee716
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/93784
Reviewed-by: Automatic_Commit_Validation_User
ARM: tegra: dma: enum for initial status of dma req

Adding new req status TEGRA_DMA_REQ_PENDING. This will be initial
status of the request when enqueued.

Change-Id: I67ee71dd0c64b6398305b86fbf186488f062e876
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/93801
Reviewed-by: Automatic_Commit_Validation_User
ARM: tegra3: Make MC early ack feature configurable.

Add a config option to configure early acknowlegement
from memory controller.

Early acknowledgement is feature of memory controller
where MC acknowledged immediately to any write requests
from CPU. To maintain mermory coherency all the read
requests are blocked till all the early-acked writes
have reached to a point of coherency.

bug 943638

Change-Id: I97f30261c4711fc338b007502b6eef7217ddb6cb
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/91477
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
tegra: video: nvmap: Make nvmap_ioctl.h userspace compatible

nvmap_ioctl.h intended to be included by both kernel and
userspace code.

Change-Id: I8cccef5e3bc02f3271f471155b2e36126c68017a
Signed-off-by: Yogish Kulkarni <yogishk@nvidia.com>
Reviewed-on: http://git-master/r/93329
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>