Start of stream buffer implementation.

Created the state necessary for the stream buffer and implemented
the stream_buffer_miss_handler(), which handles recognizing streams
and issuing the initial prefetches to start a stream buffer.

The stream_buffer_hit_handler() still needs to be implemented to
handle further prefetching in the stream. This also needs to be
tested heavily before merging back into the dev branch.
Minor commit to make sure stream buffer miss handler does not run for PREFETCH requests. :)
Stream buffer hit handler implementation.

Implemented stream_buffer_hit_handler() to handle prefetching
when the beginning of the stream buffer is used.

Also added some debug flags to print stream buffer status info
to standard error. Also added some counters to count the number
of streams generated during runtime.

Finally, added a bunch of traces to stress test the stream buffer.
These traces were generated with trace_gen.py, a configurable trace
generator for HybridSim.
Handle corner cases for stream buffer.

The stream buffer miss handler just returns immediately if the address is the first
page in memory or the last page in memory.

Additionally, some extra logging of prefetching was added. The number of prefetch hit
NOPs is now tracked, as well as the number of stream buffer hits.
Trace Based Simulation tracks throttle cycles.

Previously, TBS throttled the access stream to make sure that too
many accesses didn't go out to the hybrid memory at once. This update
tracks throttle cycles separately from cycles actually stepping through
the trace.  This prevents the issuing code from having accesses "bunch
up" and all go out at once when long stalls when events like NAND flash
accesses occur.  For example, if an access was issued every 100 cycles
in a trace and a miss causes an access to take 10000 cycles, then when
the miss returns, 100 accesses are immediately ready for issue. This
update prevents that from happening and the accesses are correctly
issued at 100 cycle intervals after the miss completes. This is more
accurate because it simulates how long the CPU would take to process
the instructions necessary to generate the memory trace (assuming the
trace was originally generated from MARSS or another mechanism modeling
a CPU). The goal of this update is to allow TBS experiments to better
estimate IPC based on a smaller number of MARSS runs. For example, we
would like to be able to run a MARSS DRAM-only run and collect the trace
and IPC. Then we could change the hybrid memory configuration and run the
trace to get a new cycle count.  The IPC could then be caused as follows:
IPC_run2 = IPC_run1 * (cycles_run2 / cycles_run1).  The error of this IPC
estimation method is an area that will be investigated in the near future.
Minor updates to configuration files.

* Update to the latest NVDIMM configuration.
* Minor update to HybridSystem.cpp to output used config files.
Minor update to .gitignore.
Added some missing config options to the nvdimm ini files.
More updates to NVDIMM ini files.

From now on, the NVDIMMSim repo located at
https://github.com/jimstevens2001/NVDIMMSim is the only "officially"
supported NVDIMMSim repo. The stable branch there is guaranteed to work
(or at least will be in the near future) with the dev and master branch
of HybridSim.  Tagged releases of NVDIMMSim will also be provided to match
the tagged releases of HybridSim and DRAMSim. Otherwise, all bets are
off. The DRAMSim and NVDIMM branches ran by Paul Rosenfeld (DRAMNinjas)
and Paul Tschirhart (watchmaker) are not necessarily compatible with
HybridSim. If you need a feature they provide, please let me know and
I can pull it into my copy of the repos. --Jim