nv30: fix inconsistent setting of push->user_priv

It's set to &nv30->bufctx everywhere else.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
glsl: propagate max_array_access through function calls

Fixes a bug where if an uniform array is passed to a function the accesses
to the array are not propagated so later all but the first vector of the
uniform array are removed in parcel_out_uniform_storage resulting in
broken shaders and out of bounds access to arrays in
brw::vec4_visitor::pack_uniform_registers.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-and-Tested-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Dominik Behr <dbehr@chromium.org>
i965: Remove never used RSR and RSL opcodes.

RSR and RSL are listed in the "Defeatured Instructions" section of the
965 PRM, Volume 4:

"The following instructions are removed from Gen4 implementation mainly
 due to implementation cost/schedule reasons.  They are candidates for
 future generations."

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Remove never used DPA2 opcode.

DPA2 is listed in the "Defeatured Instructions" section of the
965 PRM, Volume 4:

"The following instructions are removed from Gen4 implementation mainly
 due to implementation cost/schedule reasons.  They are candidates for
 future generations."

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
r600g/compute: Don't flush the cs in pipe_context::launch_grid()

This is the state tracker's responsibility.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
r600g/compute: Fix bug in compute memory pool

When adding a new buffer to the beginning of the memory pool, we were
accidentally deleting the buffer that was first in the buffer list.
This was caused by a bug in the memory pool's linked list
implementation.
docs: Add some notes on submitting patches

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Brian Paul <brianp@vmware.com>
mesa: add GL_KHR_debug functions to dispatch_sanity.cpp

Fixes 'make check' failures.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
i915g: Fix initial array index

Fixes "Out-of-bounds read" defect reported by Coverity.
i915g: Remove useless comparison

Fixes "Macro compares unsigned to 0" defect reported by Coverity.
i915g: Handle i915->batch == NULL correctly in flush

Fixes warning reported by Coverity.
i915g: Document fall-through switch

Fixes warning reported by Coverity.
gallivm: support indirect registers on both dimensions

We support indirect addressing only on the vertex index, but some
shaders also use indirect addressing on attributes. This patch
adds support for indirect addressing on both dimensions inside
gs arrays.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
mesa: Ensure gl_query_object is fully initialized.

278372b47e4db8a022d57f60302eec74819e9341 added the uninitialized pointer
field gl_query_object:Label. A free of this pointer resulted in a crash.

This patch fixes piglit regressions with swrast introduced by
6d8dd59cf53d2f47b817d79204a52bb3a46e8c77.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=69047
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
gallium, intel: Implements new __DRI_IMAGE_USE_LINEAR and PIPE_BIND_LINEAR flags to enforce no tiling.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
radeon/winsys: pad IBs to a multiple of 8 DWs

This aligns the gfx, compute, and dma IBs to 8 DW boundries.
This aligns the the IB to the fetch size of the CP for optimal
performance. Additionally, r6xx hardware requires at least 4
DW alignment to avoid a hw bug.  This also aligns the DMA
IBs to 8 DW which is required for the DMA engine.  This
alignment is already handled in the gallium driver, but that
patch can be removed now that it's done in the winsys.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
CC: "9.2" <mesa-stable@lists.freedesktop.org>
CC: "9.1" <mesa-stable@lists.freedesktop.org>
r600g: remove DMA padding

This is now handled in the winsys.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: add berlin pci ids

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
ilo: preliminary GEN 7.5 support

This is based on grepping for brw->is_haswell in i965 to see how GEN 7.5
differs from GEN 7.  Slightly tested with Xonotic and some Mesa demos.
docs: initial 9.3 release notes file

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>