Advanced Debug System VPI simulation.
orpsoc_top -- The standard JTAG TAP must be used.
              change orpsoc_defines.v
orpsoc_testbench -- dbg_comm_vpi module calls tasks defined in jp-io-vpi.so
              and provides JTAG signals such as TMS, TCK, etc.

Start simulation by running 'make rtl-test VPI=1' in $(BOARD_ROOT)/sim/run.
and run 'adv_jtag_bridge vpi' at ~.
    TODO : The adv_jtag_bridge reports timeout error.
delete variable initial value in testbench file
[temp] JTAG TAP can be recognized, but "Burst read timed out."
reset signal fixed; sim scripts added.
Merge branch 'adv_debug_sys_vpi' into Standard_JTAG_TAP
Boot from flash.
	wb_flash.v is added. It's a simple file modified from opencores
		wb_flash project. It's connected to the bytebus. Only read
		function is tested(write function not).
	A new option for bootrom.S is added 'BOOTROM_PARALLEL_FLASH'.
		It reads data from flash and stores it to RAM, and then jump
		to reset address. The first word of the flash data is size
		of the binary image. And it's stored in big-endian format.