[SparcV9] Enable custom lowering of DYNAMIC_STACKALLOC in sparc64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195573 91177308-0d34-0410-b5e6-96231b3b80d8
[SparcV9]: Do not emit .register directives for global registers that are clobbered by calls but not used in the function itself.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195574 91177308-0d34-0410-b5e6-96231b3b80d8
[Sparc]: Implement LEA pattern for sparcv9.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195575 91177308-0d34-0410-b5e6-96231b3b80d8
[Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of sethi+or. This generates correct code for both sparc32 and sparc64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195576 91177308-0d34-0410-b5e6-96231b3b80d8
Output a bit more information in the debug printing for MBP. This was
useful when analyzing parts of zlib's behavior here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195588 91177308-0d34-0410-b5e6-96231b3b80d8
SparcFrameLowering.cpp: Prune 'DL' [-Wunused-variable]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195590 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed a bug about disassembling AArch64 post-index load/store single element instructions.
ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
    echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
will be disassembled into the same instruction st1 {v0b}[0], [x0], x0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195591 91177308-0d34-0410-b5e6-96231b3b80d8
Don't look past volatile loads.

A volatile load should block us from trying to coalesce stores.
PR18023

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195599 91177308-0d34-0410-b5e6-96231b3b80d8
X86: enable AVX2 under Haswell native compilation

Patch by Adam Strzelecki

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195632 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed tryFoldToZero() for vector types that need expansion.

Summary:
Moved the requirement for SelectionDAG::getConstant() to return legally
typed nodes slightly earlier. There were two optional DAGCombine passes
that were missed out and were required to produce type-legal DAGs.

Simplified a code-path in tryFoldToZero() to use SelectionDAG::getConstant().
This provides support for both promoted and expanded vector types whereas the
previous code only supported promoted vector types.

Fixes a "Type for zero vector elements is not legal" assertion detected by
an llvm-stress generated test.

Reviewers: resistor

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2251

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195635 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r195599 as it broke the builds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195636 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM] Enable FeatureMP for Cortex-A5 by default.

Patch by Oliver Stannard.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195640 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: remove unused patterns.

There is no sane way for an LEApcrel (= single ADR) instruction to generate a
global address on any ARM target I know of. Fortunately, no-one was trying to
any more, but there were vestigial patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195644 91177308-0d34-0410-b5e6-96231b3b80d8
Make helper function static.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195650 91177308-0d34-0410-b5e6-96231b3b80d8
Refactor to make the .bss, .data and .text sections available for other uses.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195653 91177308-0d34-0410-b5e6-96231b3b80d8
Fix .comm and .lcomm on COFF.

These should not use COMDATs. GNU as uses .bss for .lcomm and section 0 for
.comm.

Given

static int a;
int b;

MSVC puts both in .bss. This patch then puts both .comm and .lcomm on .bss. With
this change we agree with gas on .lcomm, are much closer on .comm and clang-cl
matches msvc on the above example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195654 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: remove special cases for Darwin dynamic-no-pic mode.

These are handled almost identically to static mode (and ELF's global address
materialisation), except that a symbol may have "$non_lazy_ptr" appended. This
can be handled by passing appropriate flags along with the instruction instead
of using entirely separate pseudo-instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195655 91177308-0d34-0410-b5e6-96231b3b80d8
Fix indentation typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195660 91177308-0d34-0410-b5e6-96231b3b80d8
Unrevert r195599 with testcase fix.

I'm not sure how it was checking for the wrong values...
PR18023.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195670 91177308-0d34-0410-b5e6-96231b3b80d8
ARM integrated assembler generates incorrect nop opcode

This patch fixes a bug in the assembler that was causing bad code to
be emitted.  When switching modes in an assembly file (e.g. arm to
thumb mode) we would always emit the opcode from the original mode.

Consider this small example:

$ cat align.s
.code 16
foo:
  add r0, r0
.align 3
  add r0, r0

$ llvm-mc -triple armv7-none-linux align.s -filetype=obj -o t.o
$ llvm-objdump -triple thumbv7 -d t.o
Disassembly of section .text:
foo:
       0:       00 44         add     r0, r0
       2:       00 f0 20 e3   blx #4195904
       6:       00 00         movs    r0, r0
       8:       00 44         add     r0, r0

This shows that we have actually emitted an arm nop (e320f000)
instead of a thumb nop. Unfortunately, this encodes to a thumb
branch which causes bad things to happen when compiling assembly
code with align directives.

The fix is to notify the ARMAsmBackend when we switch mode. The
MCMachOStreamer was already doing this correctly. This patch makes
the same change for the MCElfStreamer.

There is still a bug in the way nops are emitted for alignment
because the MCAlignment fragment does not store the correct mode.
The ARMAsmBackend will emit nops for the last mode it knew about. In
the example above, we still generate an arm nop if we add a `.code
32` to the end of the file.

PR18019


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195677 91177308-0d34-0410-b5e6-96231b3b80d8