Fix for Ivy Bridge link training problems
Fix UCF due to different location of GTP transceivers.
Fix Wishbone interface typos/leftovers.
Fix another Wishbone interface typos/leftovers
Fix non-working FIFOs reset in simulation due to duplicated entity names
Relax CASE conditions in TAG multiplexer for better synthesis and improved timing
Update PCIe core to v1.10 and change BAR settings.
All BARs use now 64 bit addressing. This also means following changes:
BAR1 -> BAR2, added prefetching option because we only have DDR memory
behind it without any read/write access side effects.
BAR2 -> BAR4, changed size to 2 GB.
Update PCIe testbench for 64 bit addressing
Fix project to work with 64 bit addressing.
There are 2 kinds of fixes:
- incorrect definitions of specific bit fields placement in packet
  headers
- wrong/hardcoded info of BAR values

Also, update top file for additional reset signal in PCIe core 1.10.
Update speed grade to match AFC FPGAs