Updates for device worker development
adapt/os/ocpios/linux/src/OcpiOsEther.cxx: strict header fix for zync arm compiler
core/local/util/property/include/OcpiUtilProperty.h: put sub32 attribute in each property
core/local/util/property/src/OcpiUtilProperty.cxx: ditto
generic_env.sh: remove -c90 for now from CFLAGS
hdl/assemblies/tb_bias_vhdl/Makefile: change to be synthesizable
hdl/assemblies/tb_bias_vhdl/tb_bias_vhdl.xml: change to be synthesizable
hdl/assemblies/tb_bias_vhdl/tb_bias_vhdl_cont.xml: ditto
hdl/primitives/bsv/bsv_pkg.vhd: add component decl for SyncResetA for vhdl access
tools/cdk/include/hdl/hdl-pre.mk: only look for wildcard source files in workers
tools/cdk/include/hdl/hdl-worker.mk: allow packages in worker makefiles
tools/cdk/include/hdl/xsim.mk: force timescale for vivado sim
tools/cdk/include/hdl/xst.mk: get rid of extra spaces in library list
tools/cdk/include/util.mk: correct the default value of CompiledSourceFiles
tools/cdk/include/xxx-worker.mk: alloc package decls in worker makefiles
tools/cdk/ocpigen/bin/src/ocpigen_main.cxx: support direct package spec via -p option
tools/cdk/ocpigen/ocpigen/include/wip.h: add support for differential signals and record signals
-- and add support for a mix of nonraw and raw properties
-- add support for signals in specs
tools/cdk/ocpigen/ocpigen/src/wip_HDL.cxx: ditto
tools/cdk/ocpigen/ocpigen/src/wip_parse.cxx: ditto
hdl/platforms/xsim_pf/Makefile: reorder source files with "main" first
tools/cdk/include/hdl/hdl-make.mk: debug hook