DAGCombiner: fix use-counting issue when forming zextload

DAGCombiner was counting all uses of a load node  when considering whether it's
worth combining into a zextload. Really, it wants to ignore the chain and just
count real uses.

rdar://problem/13896307

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185419 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed alignment of code sections in the JIT mode. Added a test to the JITMemoryManager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185421 91177308-0d34-0410-b5e6-96231b3b80d8
Fix ARM EHABI compact model 1 and 2 without handlerdata.

According to ARM EHABI section 9.2, if the
__aeabi_unwind_cpp_pr1() or __aeabi_unwind_cpp_pr2() is
used, then the handler data must be emitted after the unwind
opcodes.  The handler data consists of several words, and
should be terminated by zero.

In case that the .handlerdata directive is not specified by
the programmer, we should emit zero to terminate the handler
data.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185422 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Fix instruction selection for zext, mkmsk instructions.

r182680 replaced CountLeadingZeros_32 with a template function
countLeadingZeros that relies on using the correct argument type to give
the right result. The type passed in the XCore backend after this
revision was incorrect in a couple of places.

Patch by Robert Lytton.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185430 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Add the MVC instruction

This is the first use of D(L,B) addressing, which required a fair bit
of surgery.  For that reason, the patch just adds the instruction
definition and the associated assembler and disassembler support.
A later patch will actually make use of it for codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185433 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Use MVC to spill loads and stores

Try to use MVC when spilling the destination of a simple load or the source
of a simple store.  As explained in the comment, this doesn't yet handle
the case where the load or store location is also a frame index, since
that could lead to two simultaneous scavenger spills, something the
backend can't handle yet.  spill-02.py tests that this restriction kicks in,
but unfortunately I've not yet found a case that would fail without it.
The volatile trick I used for other scavenger tests doesn't work here
because we can't use MVC for volatile accesses anyway.

I'm planning on relaxing the restriction later, hopefully with a test
that does trigger the problem...

Tests @f8 and @f9 also showed that L(G)RL and ST(G)RL were wrongly
classified as SimpleBDX{Load,Store}.  It wouldn't be easy to test for
that bug separately, which is why I didn't split out the fix as a
separate patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185434 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Use DSGFR over DSGR in more cases

Fixes some cases where we were using full 64-bit division for (sdiv i32, i32)
and (sdiv i64, i32).

The "32" in "SDIVREM32" just refers to the second operand.  The first operand
of all *DIVREM*s is a GR128.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185435 91177308-0d34-0410-b5e6-96231b3b80d8
Remove address spaces from MC.

This is dead code since PIC16 was removed in 2010. The result was an odd mix,
where some parts would carefully pass it along and others would assert it was
zero (most of the object streamer for example).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185436 91177308-0d34-0410-b5e6-96231b3b80d8
[APFloat] Swap an early out check so we do not dereference str.end().

Originally if D.firstSigDigit == str.end(), we will have already dereferenced
D.firstSigDigit in the first predicate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185437 91177308-0d34-0410-b5e6-96231b3b80d8
Fix -Wsign-compare warning and remove windows-style line endings introduced by r185421

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185443 91177308-0d34-0410-b5e6-96231b3b80d8
Hexagon: Avoid unused variable warnings in Release builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185445 91177308-0d34-0410-b5e6-96231b3b80d8
Revert (most of) r185393 and r185395.

"Remove floating point computations form SpillPlacement.cpp."

These commits caused test failures in lencod on clang-native-arm-lnt.

I suspect these changes are only exposing an existing issue, but
reverting anyway to keep the bots passing while we investigate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185447 91177308-0d34-0410-b5e6-96231b3b80d8
Debug Info: cleanup

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185456 91177308-0d34-0410-b5e6-96231b3b80d8

[DebugInfo] Introduce DIEExpr variant of DIEValue to hold MCExpr values

This partially reverts r185202 and restores DIELabel to hold plain
MCSymbol references.  Instead, we add a new subclass DIEExpr of
DIEValue that can hold generic MCExpr references.

This is in preparation for supporting debug info for TLS variables
on PowerPC, where we need to describe the variable location using
a more complex expression than just MCSymbolRefExpr.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185458 91177308-0d34-0410-b5e6-96231b3b80d8

[DebugInfo] Hold generic MCExpr in AddrPool

This changes the AddrPool infrastructure to enable it to hold
generic MCExpr expressions, not just MCSymbolRefExpr.

This is in preparation for supporting debug info for TLS variables
on PowerPC, where we need to describe the variable location using
a more complex expression than just MCSymbolRefExpr.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185459 91177308-0d34-0410-b5e6-96231b3b80d8

[DebugInfo] Allow getDebugThreadLocalSymbol to return MCExpr

This allows getDebugThreadLocalSymbol to return a generic MCExpr
instead of just a MCSymbolRefExpr.

This is in preparation for supporting debug info for TLS variables
on PowerPC, where we need to describe the variable location using
a more complex expression than just MCSymbolRefExpr.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185460 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] Support TLS variables in debug info

This adds an implementation of getDebugThreadLocalSymbol for
(64-bit) PowerPC.  This needs to return a generic MCExpr
since on ppc64, we need to add a bias of 0x8000 to the
value returned by the R_PPC64_DTPREL64 relocation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185461 91177308-0d34-0410-b5e6-96231b3b80d8
Add 'REQUIRES: object-emission' to DebugInfo/inlined-arguments.ll.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185465 91177308-0d34-0410-b5e6-96231b3b80d8
SystemZ: Fold variable into assertion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185475 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLD

The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD
correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD.
This causes some confusion with the asm parser, since VK_PPC_TLSGD
is output as @tlsgd, which is then read back in as VK_TLSGD.

To avoid this confusion, this patch removes the PowerPC-specific
modifiers and uses the generic modifiers throughout.  (The only
drawback is that the generic modifiers are printed in upper case
while the usual convention on PowerPC is to use lower-case modifiers.
But this is just a cosmetic issue.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185476 91177308-0d34-0410-b5e6-96231b3b80d8