[tilegx] use "info(__LINE__)" as place marker.

  by checking these "info" instructions, it will be easier to find
where we are in JITed code.
[tilegx] Some class data members are with 4 bytes length.

  use ld4s instead of ld.
[tilegx] Cleanup mips delay slot instructions.
[tilegx] Fix a stack adjustment bug.

  after this, we could run through JITed code translated from AST tree,
but crash when returning from baseline compiler.

  add "bpt" instruction support, we could place a "bpt()" in those
place in JITed code where we are interested in, so that V8 will
stop there. (this is not normal breakpoint, it's unexpected in
gdb, so need to set $pc to $pc + 8 to continue).
[tilegx] Should use addli instead of addi.

  We need to save all callee saved regs, the stack size is > 127,
thus we need 16bit imm encoding.
[tilegx] MultiPop should match MultiPush.

  missing fp restore in MultiPop, lr gets wrong value.

  after this fix, we go further in JITed code. But looks like
crankshaft feature are mixed with base line compiler, that implement
some crankshaft code is necessary for v8 to finish initialization.