Instruction Fixing

This commit aligns the assignments in darmtbl.py, but also fixes some instructions.

CDP encoding is: {COND, 1, 1, 1, 0, CPOpc, CRn, CRd, CP#, CP, 0, CRm}

COND[4] Condition
CPOpc[4] Coprocessor Operation Code
CRn[4] Coprocessor Operand Register
CRd[4] Coprocessor Destination Register
CP#[4] Coprocessor Number
CP[3] Coprocessor Information
CRm[3] Coprocessor Operand Register

MCR/MRC encoding is: {COND, 1, 1, 1, 0, CPOpc, L, CRn, Rd, CP#, CP, 1, CRm}

CPOpc[3] = Coprocessor Operation Mode
L[1] = Load/Store bit
CRn[4] = Coprocesor source/destination register
Rd[4] = ARM Source/destination register
CP#[4] = Coprocessor Number
CP[3] = Coprocessor Information
CRm = Coprocessor Operand Register

I don't have notes on CDP2/MCR2/MRC2... don't know where you're going with these.

P is the pre/post indexing bit
U depends on instruction, up/down OR unsigned
S is set condition codes OR PSR & Force User Bit
W is the write-back bit

Hope this helps