hdl/modules/pcie/common/Manifest.py: remove wrong Manifest line
hdl/top/*/*_dsp_fmc130m_4ch/*: include acquisition core

This top file includes the wb_acq_core and the
position_calc_core modules to test the position data
acquisition with the new approach
hdl/top/ml_605/*_dsp_fmc130m_4ch/*: update Manifest file
hdl/top/ml_605/*_dsp_fmc130m_4ch/*: update constraints files

Now, the .ucf file contains constraints for the DDR3 controller,
as well as some timing constraints.

Also, added new xcf constraints file.
hdl/top/ml_605/*_dsp_fmc130m_4ch/*: update chipscope project

Mainly used for debug and cross-checking
hdl/syn/ml605/*_dsp_fmc130m_4ch/*: update syn files (timing error)

In general, the design appears to work correctly, it does not
met timing! FIXME!