[FIX] timing issue with MII phy interface

Add register stage in RMII-TO-MII converter in rx and tx direction.
This aligns the bus signals, which reduces the bus-skew below 1 ns.
Note that this increases the response delay by additional 80 ns.
[FIX] Revise timing constraints of Xilinx examples

* relax MII phy timing to avoid metastability
* omit unused Tx Error pin