updated shiftIn to support 7400 series ICs

As the code currently stands, 74HC165 Parallel to Serial 
ICs's inputs are shifted 1 more than they are designed to be. 
This means 1st parallel input is shifted out, ignored, then the 2nd input is shifted out and read, and so forth until the serial data input pin is read.

Visualization:
1  2  3  4  5  6  7  8  DS
   |_________________|
            bits read

See "Files Changed" for more information.