[PowerPC] Use multiclass to generate extended branch mnemonics

This patch removes some redundancy by generating the extended branch
mnemonics via a multiclass.

No change in behaviour expected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183685 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] Support branch mnemonics with implied CR0

The extended branch mnemonics are supposed to use an implied CR0
if there is no explicit condition register specified.  This patch
adds extra variants of the mnemonics to this effect.

Problem reported by Joerg Sonnenberger.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183686 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] Support extended sc mnemonic

A plain "sc" without argument is supposed to be treated like "sc 0"
by the assembler.  This patch adds a corresponding alias.

Problem reported by Joerg Sonnenberger.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183687 91177308-0d34-0410-b5e6-96231b3b80d8
tblgen: Assert that InstRWs doesn't grows when we don't expect it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183690 91177308-0d34-0410-b5e6-96231b3b80d8
Add a missing 'e'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183692 91177308-0d34-0410-b5e6-96231b3b80d8
X86: Stop LEA64_32r doing unspeakable things to its arguments.

Previously LEA64_32r went through virtually the entire backend thinking it was
using 32-bit registers until its blissful illusions were cruelly snatched away
by MCInstLower and 64-bit equivalents were substituted at the last minute.

This patch makes it behave normally, and take 64-bit registers as sources all
the way through. Previous uses (for 32-bit arithmetic) are accommodated via
SUBREG_TO_REG instructions which make the types and classes agree properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183693 91177308-0d34-0410-b5e6-96231b3b80d8
IndentCount is only used within NDEBUG code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183695 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unused function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183698 91177308-0d34-0410-b5e6-96231b3b80d8
Fix up comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183703 91177308-0d34-0410-b5e6-96231b3b80d8
Remove a few fixmes, the only work we're doing is getting the string
to return and this is done all over.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183704 91177308-0d34-0410-b5e6-96231b3b80d8
Fix xemacs mode line, don't put them in .cpp files (just header files). No
functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183709 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.

Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some
only support Thumb mode (M-class ones currently). This makes sure such CPUs
default to the correct mode and makes the AsmParser diagnose an attempt to
switch modes incorrectly.

rdar://14024354

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183710 91177308-0d34-0410-b5e6-96231b3b80d8
[yaml2obj] Initial ELF support.

Currently, only emitting the ELF header is supported (no sections or
segments).

The ELFYAML code organization is broadly similar to the COFFYAML code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183711 91177308-0d34-0410-b5e6-96231b3b80d8
Fix spurious semicolons.

Apparently these macros have semicolons inside of them already.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183712 91177308-0d34-0410-b5e6-96231b3b80d8
Fix dubious type name similar to member name.

Should bring bots back to life.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183715 91177308-0d34-0410-b5e6-96231b3b80d8
Whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183726 91177308-0d34-0410-b5e6-96231b3b80d8
ARMAsmBackend.cpp: Use Triple::isOSBinFormatCOFF() instead of isOSWindows().

FYI, isOSBinFormatCOFF() is as same as isOSWindows(), on trunk.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183727 91177308-0d34-0410-b5e6-96231b3b80d8
Tweak a couple of tests on win32 hosts with +Asserts.

  - Don't use assert(0), or tests may pass or fail according to assertions.
  - For now, The tests are marked as XFAIL for win32 hosts.

FIXME: Could we avoid XFAIL to specify triple in the RUN lines?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183728 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: Fix STREX/LDREX reecoding

The decoded MCInst wasn't reencoded as the same instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183729 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: Enforce decoding rules for VLDn instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183731 91177308-0d34-0410-b5e6-96231b3b80d8