target-arm: A64: add support for add, addi, sub, subi

Implement the non-carry forms of addition and subtraction
(immediate, extended register and shifted register).
This includes the code to calculate NZCV if the instruction
calls for setting the flags.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>

---
Changes:
  - remove pointless mov op (we already have a copy)
target-arm: A64: add support for move wide instructions

This patch adds emulation for the mov wide instructions
(MOVN, MOVZ, MOVK).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: add support for 3 src data proc insns

This patch adds emulation for the "Data-processing (3 source)"
family of instructions, namely MADD, MSUB, SMADDL, SMSUBL, SMULH,
UMADDL, UMSUBL, UMULH.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
Changes:
  - Use tcg ops for mul[su]h (rh comment)
target-arm: A64: implement SVC, BRK

Add decoding for the exception generating instructions, and implement
SVC (syscalls) and BRK (software breakpoint).

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
default-configs: Add config for aarch64-linux-user

Add a config for aarch64-linux-user, thereby enabling it as
a valid target.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-arm: A64: Add decoder skeleton for FP instructions

Add a top level decoder skeleton for FP instructions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: implement FMOV

Implement FMOV, ie non-converting moves between general purpose
registers and floating point registers. This is a subtype of
the floating point <-> integer instruction class.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: add preliminary support for MSR/MRS

this is very very limited: we only support
setting and getting NZCV (C4.3.10),
getting CTR_EL0 (D8.2.21) with a hardcoded value,
getting DCZID_EL0 (D8.2.23) with a hardcoded value,
getting and setting TPIDR_EL0 (D8.2.87).

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder structure, put common code
          between MSR/MRS in a separate function, add NZCV,
          add support for writing to TPIDR_EL0,
          fixed high bit of CTR_EL0]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
target-arm: A64: MRS/MSR for FPCR and FPSR access

Add FPCR and FPSR to the set of registers handled by MRS/MSR;
implemented via calls to helper functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
.travis.yml: add aarch64-linux-user target
linux-user/signal.c: dump pc when aborting

It doesn't hurt and it certainly helps when bringing up new instructions
when it breaks.
translate-a64.c: add a debug helper trace macro

This just makes it easier to drop TRACE_DECODE statements all over the
place instead of fprintfs.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v1 -> v2:
   - Make it take vaargs for fmt as not all decoders follow the dame form
target-arm: aarch64: add support for ld lit

Adds support for Load Register (literal).

from Alexander Graf <agraf@suse.de> aarch64 series 40/60

---

v3 -> v4 (ajb):
   - use new ld_gpr api

v4 -> v5 (ajb):
   - fixup commenting style
target-arm: A64: WIP support for ld/st exclusive

XXX: not up-streamable as is - still has failure modes

This implement exclusive loads/stores for aarch64 like for arm32 and
ppc.  loads remember the address and loaded value, and stores throw
an exception which uses those values to check for equality in a proper
exclusive region.

AArch64 also implements new aquire/release loads/stores without the
exclusive part, which merely imposes an ordering on memory operations.
As we run on just one CPU, that's not necessary, but could be done
e.g. by a simple heavy barrier insn.

from Alexander Graf <agraf@suse.de> aarch64 series 12/60
 and Michael Matz <matz@suse.de> aarch64-1.6 branch
 and Peter Maydell <peter.maydell@linaro.org> aarch64 clean-up

---

v3 -> v4 (ajb):
   - use new gpr_ld API

v4 -> v5 (ajb):
   - merge in later fixes from Matz
   - fix bug with using ZR for status
   - add sp alignment check
   - fixup bogus whitespace
target-arm: A64: add support for conditional compare insns

this patch adds support for C3.5.4 - C3.5.5
Conditional compare (both immediate and register)

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
ldst excl: comment out debug