Xilinx Coolrunner II HDL Hello World with inital setup
Use CLK_DIV16 CPLD clock divider by 16 to reduce counter size

- Also add simulation waveform commands
- Toplevel must use std_logic*, otherwise Testbench cannot bind to Gatelevel netlist
- Create RTL and POST simulation configurations
- Modify code to run in both RTL and POST simulation
LEDs are low-active (connected to VCC)
Programming scriptlet added

The Digilent programmer plugin does not work for me (somehow)
Show more: Use all 4 LEDs as 4-bit binary counter