ARM sched model: Add SIMD/VFP load/store instructions on Swift

Reapply 183270.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183445 91177308-0d34-0410-b5e6-96231b3b80d8
Debug Info: simplify parameter ordering preservation

Seems we emit the parameter ordering number (spuriously named 'arg
number') in the debug info, so there's no need to search through the
variable list to figure out the parameter ordering. This implementation
does 'always' do the work, even in non-optimized debug info (the
previous implementation checked the existence of the 'variables' list on
the subprogram which is only present in optimized builds).

No intended functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183446 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift"

Breaks linux build bots (I thought the problem was something else).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183447 91177308-0d34-0410-b5e6-96231b3b80d8
Fix break in r183446 - helps to increment the iterator in a loop

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183454 91177308-0d34-0410-b5e6-96231b3b80d8
Jeffrey Yasskin volunteered to benchmark the vectorizer on -O2 or -Os when compiling chrome. This patch adds a new flag to enable vectorization on all levels and not only on -O3. It should go away once we make a decision.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183456 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Rewrite an awkward loop in R600MachineScheduler

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183458 91177308-0d34-0410-b5e6-96231b3b80d8
CodeGenSchedule: smallvector.push_back(smallvector[0]) is dangerous

The element passed to push_back is not copied before the vector reallocates.
The client needs to copy the element first before passing it to push_back.

No test case, will be tested by follow-up swift scheduler model change (it
segfaults without this change).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183459 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unneeded #include.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183460 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify code. No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183461 91177308-0d34-0410-b5e6-96231b3b80d8
[Sparc]: Use cmp instruction instead of subcc to compare integers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183463 91177308-0d34-0410-b5e6-96231b3b80d8
ARM sched model: Add SIMD/VFP load/store instructions on Swift

Reapply 183270 again (because three is a magic number).

This should now no longer seg fault after r183459.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183464 91177308-0d34-0410-b5e6-96231b3b80d8
CodeGenSchedule: Use resize instead of copying a vector

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183465 91177308-0d34-0410-b5e6-96231b3b80d8
ARM sched model: Add VFP div instruction on Swift

Reapply 183271.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183472 91177308-0d34-0410-b5e6-96231b3b80d8
ARM sched model: Use the right resources for DIV

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183477 91177308-0d34-0410-b5e6-96231b3b80d8
DIBuilder: No functionality change.

Use the correct DIType when creating vector types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183484 91177308-0d34-0410-b5e6-96231b3b80d8
Don't cache the instruction info and register info objects.

These objects are internal to the TargetMachine object and may change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183485 91177308-0d34-0410-b5e6-96231b3b80d8
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183488 91177308-0d34-0410-b5e6-96231b3b80d8
[objc-arc] Ensure that the cfg path count does not overflow when we multiply TopDownPathCount/BottomUpPathCount.

rdar://12480535

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183489 91177308-0d34-0410-b5e6-96231b3b80d8
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183490 91177308-0d34-0410-b5e6-96231b3b80d8
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183491 91177308-0d34-0410-b5e6-96231b3b80d8