xfrm_algo: probe asynchronous block ciphers instead of synchronous

IPSEC uses block ciphers asynchronous, but probes only for synchronous block
ciphers and makes ealg entries only available if synchronous block cipher is
found. So with setup, where hardware crypto driver registers asynchronous
block ciphers and software crypto module is not build, ealg is not marked
as being available.

Use crypto_has_ablkcipher instead and remove ASYNC mask.

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: ctr - make rfc3686 asynchronous block cipher

Some hardware crypto drivers register asynchronous ctr(aes), which is left
unused in IPSEC because rfc3686 template only supports synchronous block
ciphers. Some other drivers register rfc3686(ctr(aes)) to workaround this
limitation but not all.

This patch changes rfc3686 to use asynchronous block ciphers, to allow async
ctr(aes) algorithms to be utilized automatically by IPSEC.

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: aesni-intel - remove rfc3686(ctr(aes)), utilize rfc3686 from ctr-module instead

rfc3686 in CTR module is now able of using asynchronous ctr(aes) from
aesni-intel, so rfc3686(ctr(aes)) in aesni-intel is no longer needed.

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: testmgr - add test vector fcrypt

fcrypt is used only as pcbc(fcrypt), but testmgr does not know this.
Use the zero key, zero plaintext pcbc(fcrypt) test vector for
testing plain 'fcrypt' to hide "no test for fcrypt" warnings.

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: x86/aes - assembler clean-ups: use ENTRY/ENDPROC, localize jump targets

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: aesni-intel - add ENDPROC statements for assembler functions

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: blowfish-x86_64: use ENTRY()/ENDPROC() for assembler functions and localize jump targets

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: camellia-x86_64/aes-ni: use ENTRY()/ENDPROC() for assembler functions and localize jump targets

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: cast5-avx: use ENTRY()/ENDPROC() for assembler functions and localize jump targets

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: cast6-avx: use ENTRY()/ENDPROC() for assembler functions

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: x86/crc32c - assembler clean-up: use ENTRY/ENDPROC

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: x86/ghash - assembler clean-up: use ENDPROC at end of assember functions

Signed-off-by: Jussi Kivilinna <jussi.kivilinn@mbnet.fi>
crypto: x86/salsa20 - assembler cleanup, use ENTRY/ENDPROC for assember functions and rename ECRYPT_* to salsa20_*

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: x86/serpent - use ENTRY/ENDPROC for assember functions and localize jump targets

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: x86/sha1 - assembler clean-ups: use ENTRY/ENDPROC

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: x86/twofish - assembler clean-ups: use ENTRY/ENDPROC, localize jump labels

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: testmgr - extend camellia test-vectors for camellia-aesni/avx2

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: tcrypt - add async cipher speed tests for blowfish and camellia

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: tcrypt - randomize speed test memory

Running speed tests on uniform memory can give better performance results than on random/real-world data. Therefore randomize memory
to be used by speed tests.

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: blowfish - add AVX2/x86_64 implementation of blowfish cipher

TODO: test performance on real hardware.

Performance tests using Intel Architecture Code Analyzer Version - 2.0.1:

Estimates assume that latencies and throughput of 256-bit AVX2 instructions
are same as of 128-bit AVX instructions, except vpgatherdd that is estimated as
following:
 *1: Dispatches 8 load uops, that can be dispatched to two load ports, and 2
     helper uops for merging loads. This also is nearly same as estimating
     case where there is only one load port with gather hardware with 4 cycles
     latency.
 *2: Dedicated gather hardware on two load ports, 1 uop with latency of 8
     cycles (can fetch parallel on two ports) + 2 helper uops.
 *3: Dedicated gather hardware on two load port, 1 uop with latency of 4
     cycles (can fetch parallel on two ports) + 2 helper uops.

blowfish-32way, cycles/byte:
 *1:	4.22
 *2:	3.76
 *3:	2.62

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>