Revert "ARM: OMAP4: tuna: turn off IO wakeup on touch screen IRQ pin"

This reverts commit e8d1ee623cb40e468741ef2bdb7e2ad6303f2847.

For now, WAKEUPENABLE needs to be set on the touchscreen irq pad
to allow it to wake the device from OSWR during idle.

Change-Id: If7fb7ce8c6492694893fa68872bf1fdf149bc476
Signed-off-by: Colin Cross <ccross@android.com>
ARM: OMAP2+: arch/arm/mach-omap2/devices.c: introduce missing kfree

pdata needs to be freed before leaving the function in an error case.

A simplified version of the semantic match that finds the problem is as
follows: (http://coccinelle.lip6.fr)

// <smpl>
@r exists@
local idexpression x;
statement S;
identifier f1;
position p1,p2;
expression *ptr != NULL;
@@

x@p1 = \(kmalloc\|kzalloc\|kcalloc\)(...);
...
if (x == NULL) S
<... when != x
     when != if (...) { <+...x...+> }
x->f1
...>
(
 return \(0\|<+...x...+>\|ptr\);
|
 return@p2 ...;
)

@script:python@
p1 << r.p1;
p2 << r.p2;
@@

print "* file: %s kmalloc %s return %s" % (p1[0].file,p1[0].line,p2[0].line)
// </smpl>

Signed-off-by: Julia Lawall <julia@diku.dk>
Signed-off-by: Tony Lindgren <tony@atomide.com>
omap: Adding opp functions to gpu platform data.

omap: Adding opp functions to gpu platform data.

This is required for providing opp framework access to SGX kernel module.

Change-Id: Ie968a6c51ac636b70909257be4c51430c4cc3d48
Signed-off-by: Rogelio Garcia <rgarcia@ti.com>
OMAP: dmtimer: Fix memory leak on dmtimer error

Change-Id: I858c24a21410f2c1c85b1b8b2c1fc4dc5d3c1e6d
Signed-off-by: Jared Suttles <jsuttles@motorola.com>
OMAP: dmtimer: Fix timer handling logic for non loses_context timers

The use of the enabled flag is currently tightly coupled with the
loses_context flag on the timer struct. This change makes the enabled
flag behave more sanely without consideration of the loses_context flag.

Change-Id: I9d33bb4cc3fd7917ad493adde75cf57cb240b106
Signed-off-by: Jared Suttles <jsuttles@motorola.com>
ARM: OMAP4: EMIF: implementation of errata i735 for PM timer

EMIF Power Management timer for Self Refresh will put the external SDRAM
in Self Refresh mode after the EMIF is idle for number of DDR clock cycles
that is set with REG_SR_TIM. The minimal value starts at 16 cycles.
However due to Errata i735, the minimal value is 512 DDR cycles as it is
required at OPP100 frequency.

Change-Id: If0748903580877aa4c1803f47e9134ee60c1dd75
Signed-off-by: Konstantyn Shlyakhovoy <x0155534@ti.com>
modified for tuna by faux123
OMAP4: EMIF: unify access to EMIF_PWR_MGMT_CTRL.REG_LP_MODE

OMAP4: EMIF: unify access to EMIF_PWR_MGMT_CTRL.REG_LP_MODE

Use set_lp_mode for changing EMIF_PWR_MGMT_CTRL.REG_LP_MODE.

Change-Id: Ia6410f97c8937faee6fbfc335d5d1158de41583b
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>