add avalon bus interface
mmu: hardware reload pte changes

Makes the PTE compliant with the suggestion outlined in
http://lists.openrisc.net/pipermail/openrisc/2013-July/001806.html
Also, properly interpret the L flag and marks the PL1 flag in
the translate register as pointed out is necessary in
http://lists.openrisc.net/pipermail/openrisc/2013-July/001810.html
The actual PL1 flag is not completely implemented yet
and things are still subject to change.
immu: move spr accesses to the first port of tlb dprams

This is to free up the second port to be able to hook-up
huge page indexing to that.
This renames the tlb_reload_busy signal to just busy, since it now
assert on spr accesses also, stalling the fetcher while "wrong"
address is being fetched/written to the tlb.
mmu: fix "typo" in comment about PTEs in PTE table