spi driver from 2011-12-01: spi: tegra: fix uninitialized values and if statement
spi: tegra: Select best clock source for required rate

Providing the different clock source option through platform data
to select best clock source based on required interface frequency.

bug 851642

Original-Change-Id: I18bf817b63cf1afac7db3969f266cc5fcaeee81e
Reviewed-on: http://git-master/r/41226
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: Ra4e4573414ef2c4e72cdcb4cd5625e242cfb4ec6

Conflicts:
	drivers/spi/spi_slave_tegra.c
some olympus specific parts for spi
drivers: spi: tegra: Add runtime PM support

Bug 886806
Original commit: http://git-master/r/59905

Change-Id: Ia8d64f3810d6157c6029180cd9a3cf98c2d3cb4c
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/74896
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Conflicts:
	drivers/spi/spi-tegra.c
spi: tegra: Make sure SCLK frequency to be in minimum require value.

Making sure that SCLK frequency should be maintain on minimum
require value during spi transfer. This is require to proper
functioning of spi controller.

bug 949393

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/89526

Cherry-picked from commit
	7d83f658b39b2ab1a5105eec7649246fddea7325

Change-Id: I60fa0fef98e5f2882c646c29e1773194deddd6da
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/90296
Reviewed-by: Automatic_Commit_Validation_User
spi: tegra: Handles suspend when spi transfer is in progress

Avoiding the suspend of the system if the spi transfer is
in progress for current transfer queue.

bug 864987

Reviewed-on: http://git-master/r/56599
(cherry picked from commit 0ba8ed371f2937a095752a0edbc15ed75664644a)
Change-Id: Ife7ae8a7d66a66d047ee2c8829d16017571b4d58
Reviewed-on: http://git-master/r/57001
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: Rc66d6c7ae51ea6709d5e47331fef30c87029b343
change spi... to spin...
spi: tegra: Move clock controls api out of spin lock

The clock control apis can be sleepable in tegra platform as
spi require frequency/voltage boosting.
Moving the clock controls api out of spin lock context.

bug 874841

Reviewed-on: http://git-master/r/56869
(cherry picked from commit b316a4e4fd82f1af9af920079119c56bf271c3be)
Change-Id: I8fc824de02cb3af54f6331efa0500c79e806bb03
Reviewed-on: http://git-master/r/57315
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R601bd69547ec2612f42d24da29a2f8a5d3fb1fb8

Conflicts:
	drivers/spi/spi-tegra.c
SPI: tegra: Pass rx data only to req bit length

When fifo is read, it can contain valid data bits and random bits
in rest of the fifo.
Reading only valid bits from fifo and resetting rest to zero
before sending to client.

Change-Id: I961279048aada6087b323ab6730bf72706730917
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/70534
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
spi: tegra: use run time pm apis for clock control

Used run time apis for clock controls i.e. clock enable/
disable in place of direct clock apis.
Using of runtime pm api was already implemented but it was
missed on probe where it was calling clock_disable.
Fixing this issue.

bug 928541

Change-Id: I511467bd1cbe05f2a05d219d19236426a30d05d5
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/78156
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com>
spi: tegra: dequeue dma req using tegra_dma_dequeue_req()

The dma client should use the tegra_dma_dequeue_req() for
dequeue the dma request.

Change-Id: I1f433c85ffec997d8c608e08509c48c72b27120a
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/77804
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
spi: tegra: Add Dma/cpu buffer synchronisation

When dma coherant buffer need to be access by cpu or apb dma,
it is require to calling the dma_sync_single_for_cpu() when cpu
wants to access it and dma_sync_single_for_device() when dma
wants to access the buffer.

Change-Id: I62fc7fced782f3fc2d145c0d5416a4c8cbe30715
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/85138
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
spi: tegra: checkpatch cleanups

Removing checkpatch error and warnings from spi driver
resulted from checkpatch.

Change-Id: I92160e802781b583048f46a93dee7d2465689cc0
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/85163
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
spi: tegra: Fix CS status properly in spi setup

Fixing the logic to clear/set spi cs level on default command
register.

Change-Id: I55e130ecb02dae6e11ad7048730ed11df9848e94
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/86888
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
spi: tegra: Use tegra_dma_cancel() to abort request

To terminate request from dma, use the tegra_dma_cancel() inplace of
tegra_dma_dequeue().
The api tegra_dma_dequeue() is getting to be obsolete.

Change-Id: I297e67433a2118377ecb9b028dcf8fa82e09f0e2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/91752
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com>
Tested-by: Ashwini Ghuge <aghuge@nvidia.com>
spi: tegra: register interrupt as ONESHOT

The Tegra spi's engine is design as it generates interrupt
when any error occurs and it keep transferring data. It does
not stop the engine once error occurred and interrupt generated.
This may cause reentry of ISR as on error case, isr get called
where it clears interrupt and because it is still in progress,
it again interrupts and schedule the thread.
The second time scheduling of the isr/thread can cause the issue
in queue management and sw state.
So Making the interrupt as ONESHOT so that the interrupt will not
get schedule until the engine is reset in error case.

Change-Id: I96daaf50102aede93164c82b7f6da235d0a7fbfc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/101547
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com>
Tested-by: Jui Chang Kuo <jckuo@nvidia.com>
spi: tegra: correct directions when syncing buffer for device/dma.

The Tx buffer to be synced with the direction of DMA_TO_DEVICE and
Rx buffer should be synced with direction of DMA_FROM_DEVICE.

bug 959947

Change-Id: I490a93e05723e3114c8ae3c640bb7eff23bcc75d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/103095
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
spi: tegra: cleanup in runtime_pm implementation.

Cleaning up runtime pm implementation for the driver.
There is lots of duplicate code which is not require as
it is handled in the runtime framework.

Change-Id: I4494cdd3518cbcb90f24fb3387f38c9859b4f957
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/102206
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Conflicts:
	drivers/spi/spi-tegra.c
spi: tegra: synchronize PPSB late write

When any write is made to PPSB register, it take time
to actual happen in the register due to ARM-PPSB design.
Delay or readback is required to make sure that write is
completed. There is no worst case guaranteed delay and hence
doing the register read to make write completes actually.

Change-Id: Iefd25115e1a9f02c64e83f11a4e249ad9d086d16
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/102207
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
spi: tegra: fix fifo_depth to 32.

Slink controller have the fifo depth of 32 words in
rx and tx side. But some of places it was taken the
value as 4. Fixing this to 32 words.

Change-Id: I262127c59241ce75d4385464c21ee733a48b1475
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/104463
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Stephen Warren <swarren@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>