2013-03-20  Tilo Schwarz  <tilo@tilo-schwarz.de>

        PR libfortran/48618
        * io/open.c (st_open): Raise error for unit number < 0 only if
        unit number does not exist already.

2013-03-20  Tilo Schwarz  <tilo@tilo-schwarz.de>

        PR libfortran/48618
        * gfortran.dg/open_negative_unit_1.f90: New.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196805 138bc75d-0d04-0410-961f-82ee72b054a4
2013-03-20  Tilo Schwarz  <tilo@tilo-schwarz.de>

        PR libfortran/51825
        * io/list_read.c (nml_read_obj): Don't end the component loop on
        a nested derived type, but continue with the next loop iteration.
        (nml_get_obj_data): Don't move the first_nl pointer further in
        the list if a qualifier was found.

2013-03-20  Tilo Schwarz  <tilo@tilo-schwarz.de>

        PR libfortran/51825
        * gcc/testsuite/gfortran.dg/namelist_77.f90: New.
        * gcc/testsuite/gfortran.dg/namelist_78.f90: New.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196806 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/
	* config/mips/constraints.md (T): Rename to...
	(Yf): ...this.
	(U): Rename to...
	(Yd): ...this.
	* config/mips/mips.md (*movdi_64bit, *movdi_64bit_mips16)
	(*mov<mode>_internal, *mov<mode>_mips16): Update accordingly.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196807 138bc75d-0d04-0410-961f-82ee72b054a4
2013-03-20  Richard Biener  <rguenther@suse.de>

	* tree-vect-loop-manip.c (slpeel_can_duplicate_loop_p): Do not
	check whether an SSA update is needed.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196810 138bc75d-0d04-0410-961f-82ee72b054a4
2013-03-20  Richard Biener  <rguenther@suse.de>

	* cfgloop.c (verify_loop_structure): Streamline and avoid
	ICEing on corrupt loop tree.
	* graph.c (draw_cfg_nodes_for_loop): Avoid ICEing on corrupt
	loop tree.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196811 138bc75d-0d04-0410-961f-82ee72b054a4
2013-03-20  Richard Biener  <rguenther@suse.de>

	* tree-ssa-structalias.c (struct variable_info): Add pointer
	to the first field of an aggregate with sub-vars.  Make
	this and the pointer to the next subfield its ID.
	(vi_next): New function.
	(nothing_id, anything_id, readonly_id, escaped_id, nonlocal_id,
	storedanything_id, integer_id): Increment by one.
	(new_var_info, get_call_vi, lookup_call_clobber_vi,
	get_call_clobber_vi): Adjust.
	(solution_set_expand): Simplify and speedup.
	(solution_set_add): Inline into ...
	(set_union_with_increment): ... this.  Adjust accordingly.
	(do_sd_constraint): Likewise.
	(do_ds_constraint): Likewise.
	(do_complex_constraint): Simplify.
	(build_pred_graph): Adjust.
	(solve_graph): Likewise.  Simplify and speedup.
	(get_constraint_for_ssa_var, get_constraint_for_ptr_offset,
	get_constraint_for_component_ref, get_constraint_for_1,
	first_vi_for_offset, first_or_preceding_vi_for_offset,
	create_function_info_for, create_variable_info_for_1,
	create_variable_info_for, intra_create_variable_infos): Adjust.
	(init_base_vars): Push NULL for ID zero.
	(compute_points_to_sets): Adjust.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196812 138bc75d-0d04-0410-961f-82ee72b054a4
	PR bootstrap/56656
	* config/i386/i386.md (*movdi_internal): Handle broken assemblers
	that require movd instead of movq.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196813 138bc75d-0d04-0410-961f-82ee72b054a4
2013-03-20  Tobias Burnus  <burnus@net-b.de>

        * i-fortra.ads: Update comment, add Ada 2012's optional
        Star and Kind data types for enhanced interoperability.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196814 138bc75d-0d04-0410-961f-82ee72b054a4
Don't XFAIL gfortran.dg/do_1.f90 (PR fortran/54932)

	PR fortran/54932
	* gfortran.dg/do_1.f90: Don't xfail.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196821 138bc75d-0d04-0410-961f-82ee72b054a4
gcc:

2013-03-13  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
	    Steven Bosscher <steven@gcc.gnu.org>

	PR rtl-optimization/56605
	* loop-iv.c (implies_p): Handle equal RTXs and subregs.

gcc/testsuite:

2013-03-13  Bill Schmidt  wschmidt@linux.vnet.ibm.com>

	PR rtl-optimization/56605
	* gcc.target/powerpc/pr56605.c: New.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196823 138bc75d-0d04-0410-961f-82ee72b054a4
2013-03-20  Richard Biener  <rguenther@suse.de>

	* tree-inline.c (copy_tree_body_r): Sync MEM_REF code with
	remap_gimple_op_r.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196824 138bc75d-0d04-0410-961f-82ee72b054a4
2013-03-20  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/56661
	* tree-ssa-sccvn.c (visit_use): Only value-number calls if
	the result does not have to be distinct.

	* gcc.dg/torture/pr56661.c: New testcase.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196825 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/
2013-03-20  Catherine Moore  <clm@codesourcery.com>
	    Maciej W. Rozycki  <macro@codesourcery.com>
	    Tom de Vries  <tom@codesourcery.com>
	    Nathan Sidwell <nathan@codesourcery.com>
	    Iain Sandoe  <iain@codesourcery.com>
	    Nathan Froyd  <froydnj@codesourcery.com>
	    Chao-ying Fu <fu@mips.com>

	* doc/extend.texi: (micromips, nomicromips, nocompression):
	Document new function attributes. 
	* doc/invoke.texi (minterlink-compressed, mmicromips,
	m14k, m14ke, m14kec): Document new options.
	(minterlink-mips16): Update documentation.
	* doc/md.texi (ZC, ZD): Document new constraints.
	* configure.ac (gcc_cv_as_micromips): Check if linker
	supports the .set micromips directive.
	* configure: Regenerate.
	* config.in: Regenerate.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/micromips.md: New file.
	* constraints.md (ZC, ZD): New constraints.
	* config/mips/predicates.md (movep_src_register): New predicate.
	(movep_src_operand): New predicate.
	(non_volatile_mem_operand): New predicate.
	* config/mips/mips.md (multimem): New type.
	(length): Differentiate between 17-bit and 18-bit branch offsets.
	(MOVEP1, MOVEP2): New mode iterator.
 	(mov_<load>l): Use ZC constraint.
	(mov_<load>r): Likewise.
	(mov_<store>l): Likewise.
	(mov_<store>r): Likewise.
	(*branch_equality<mode>_inverted): Add microMIPS support.
	(*branch_equality<mode>): Likewise.
	(*jump_absolute): Likewise.
	(indirect_jump_<mode>): Likewise.
	(tablejump_<mode>): Likewise.
	(<optab>_internal): Likewise.
	(sibcall_internal): Likewise.
	(sibcall_value_internal): Likewise.
	(prefetch): Use constraint ZD.
	* config/mips/mips.opt (minterlink-compressed): New option.
	(minterlink-mips16): Now an alias for minterlink-compressed.
	(mmicromips): New option.
	* config/mips/sync.md (sync_compare_and_swap<mode>): Use ZR constraint.
	(compare_and_swap_12): Likewise.
	(sync_add<mode>): Likewise.
	(sync_<optab>_12): Likewise.
	(sync_old_<optab>_12): Likewise.
	(sync_new_<optab>_12): Likewise.
	(sync_nand_12): Likewise.
	(sync_old_nand_12): Likewise.
	(sync_new_nand_12): Likewise.
	(sync_sub<mode>): Likewise.
	(sync_old_add<mode>): Likewise.
	(sync_old_sub<mode>): Likewise.
	(sync_new_add<mode>): Likewise.
	(sync_new_sub<mode>): Likewise.
	(sync_<optab><mode>): Likewise.
	(sync_old_<optab><mode>): Likewise.
	(sync_new_<optab><mode>): Likewise.
	(sync_nand<mode>): Likewise.
	(sync_old_nand<mode>): Likewise.
	(sync_new_nand<mode>): Likewise.
	(sync_lock_test_and_set<mode>): Likewise.
	(test_and_set_12): Likewise.
	(atomic_compare_and_swap<mode>): Likewise.
	(atomic_exchange<mode>_llsc): Likewise.
	(atomic_fetch_add<mode>_llsc): Likewise.
	* config/mips/mips-cpus.def (m14kc, m14k): New processors.
	* config/mips/mips-protos.h (umips_output_save_restore): New prototype.
	(umips_save_restore_pattern_p): Likewise.
	(umips_load_store_pair_p): Likewise.
	(umips_output_load_store_pair): Likewise.
	(umips_movep_target_p): Likewise.
	(umips_12bit_offset_address_p): Likewise.
	* config/mips/mips.c (MIPS_MAX_FIRST_STEP): Update for microMIPS.
	(mips_base_mips16): Rename this...
	(mips_base_compression_flags): ...to this. Update all uses.
	(mips_attribute_table): Add micromips, nomicromips and nocompression.
	(mips_mips16_decl_p): Delete.
	(mips_nomips16_decl_p): Delete.
 	(mips_get_compress_on_flags): New function.
	(mips_get_compress_off_flags): New function.
	(mips_get_compress_mode): New function.
	(mips_get_compress_on_name): New function.
	(mips_get_compress_off_name): New function.
	(mips_insert_attributes): Support multiple compression types.
	(mips_merge_decl_attributes): Likewise.
	(umips_12bit_offset_address_p): New function.
	(mips_start_function_definition): Emit .set micromips directive.
	(mips_call_may_need_jalx_p): New function.
	(mips_function_ok_for_sibcall): Add microMIPS support.
	(mips_print_operand_punctuation): Support short delay slots and
	compact jumps.
	(umips_swm_mask, umips_swm_encoding): New.
	(umips_build_save_restore): New function.
	(mips_for_each_saved_gpr_and_fpr): Add microMIPS support.
	(was_mips16_p): Remove.
	(old_compression_mode): New.
	(mips_set_compression_mode): New function.
	(mips_set_current_function): Add microMIPS support.
	(mips_option_override): Likewise.
	(umips_save_restore_pattern_p): New function.
	(umips_output_save_restore): New function.
	(umips_load_store_pair_p_1): New function.
	(umips_load_store_pair_p): New function.
	(umips_output_load_store_pair_1): New function.
	(umips_output_load_store_pair): New function.
	(umips_movep_target_p) New function.
	(mips_prepare_pch_save): Add microMIPS support.
	* config/mips/mips.h (TARGET_COMPRESSION): New.
	(TARGET_CPU_CPP_BUILTINS): Update macro
	to use new compression flags and to support microMIPS.
	(MIPS_ISA_LEVEL_SPEC): Add m14k processors.
	(MIPS_ARCH_FLOAT_SPEC): Likewise.
	(ISA_HAS_LWXS): Include TARGET_MICROMIPS.
	(ISA_HAS_LOAD_DELAY): Exclude TARGET_MICROMIPS.
	(ASM_SPEC): Support mmicromips and mno-micromips.
	(M16STORE_REG_P): New macro.
	(MIPS_CALL): Support TARGET_MICROMIPS.
	(MICROMIPS_J): New macro.
	(mips_base_mips16): Rename this...
	(mips_base_compression_flags): ...to this.
	(UMIPS_12BIT_OFFSET_P): New macro.
	* config/mips/t-sde: (MULTILIB_OPTIONS): Add microMIPS.
	(MULTILIB_DIRNAMES): Likewise.
libgcc/
2013-03-20  Catherine Moore  <clm@codesourcery.com>
	    Joseph Myers  <joseph@codesourcery.com>
	    Chao-ying Fu  <fu@mips.com>

	* config/mips/mips16.S:  Don't build for microMIPS.
	* config/mips/linux-unwind.h: Handle microMIPS frame.
	* config/mips/crtn.S (fini, init): New labels.
gcc/testsuite/
2013-03-20  Catherine Moore  <clm@codesourcery.com>
	    Richard Sandiford <rdsandiford@googlemail.com>

	* gcc.target/mips/mips.exp: Add microMIPS support.
	* gcc.target/mips/umips-movep-2.c: New test.
	* gcc.target/mips/umips-lwp-2.c: New test.
	* gcc.target/mips/umips-swp-5.c: New test.
	* gcc.target/mips/umips-constraints-1.c: New test.
	* gcc.target/mips/umips-lwp-3.c: New test.
	* gcc.target/mips/umips-swp-6.c: New test.
	* gcc.target/mips/umips-constraints-2.c: New test.
	* gcc.target/mips/umips-save-restore-1.c: New test.
	* gcc.target/mips/umips-lwp-4.c: New test.
	* gcc.target/mips/umips-swp-7.c: New test.
	* gcc.target/mips/umips-save-restore-2.c: New test.
	* gcc.target/mips/umips-lwp-swp-volatile.c: New test.
	* gcc.target/mips/umips-lwp-5.c: New test.
	* gcc.target/mips/umips-save-restore-3.c: New test.
	* gcc.target/mips/umips-lwp-6.c: New test.
	* gcc.target/mips/umips-swp-1.c: New test.
	* gcc.target/mips/umips-lwp-7.c: New test.
	* gcc.target/mips/umips-swp-2.c: New test.
	* gcc.target/mips/umips-lwp-8.c: New test.
	* gcc.target/mips/umips-swp-3.c: New test.
	* gcc.target/mips/umips-movep-1.c: New test.
	* gcc.target/mips/umips-lwp-1.c: New test.
	* gcc.target/mips/umips-swp-4.c: New test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196828 138bc75d-0d04-0410-961f-82ee72b054a4
2013-03-20  Marc Glisse  <marc.glisse@inria.fr>

	PR tree-optimization/56355
gcc/
	* fold-const.c (tree_binary_nonnegative_warnv_p) <MULT_EXPR>:
	Also handle integers with undefined overflow.

gcc/testsuite/
	* gcc.dg/pr56355-1.c: New file.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196829 138bc75d-0d04-0410-961f-82ee72b054a4
[gcc]
2013-03-20  Pat Haugen <pthaugen@us.ibm.com>

	* config/rs6000/predicates.md (indexed_address, update_address_mem
	update_indexed_address_mem): New predicates.
	* config/rs6000/vsx.md (vsx_extract_<mode>_zero): Set correct "type"
	attribute for load/store instructions.
	* config/rs6000/dfp.md (movsd_store): Likewise.
	(movsd_load): Likewise.
	* config/rs6000/rs6000.md (zero_extend<mode>di2_internal1): Likewise.
	(unnamed HI->DI extend define_insn): Likewise.
	(unnamed SI->DI extend define_insn): Likewise.
	(unnamed QI->SI extend define_insn): Likewise.
	(unnamed QI->HI extend define_insn): Likewise.
	(unnamed HI->SI extend define_insn): Likewise.
	(unnamed HI->SI extend define_insn): Likewise.
	(extendsfdf2_fpr): Likewise.
	(movsi_internal1): Likewise.
	(movsi_internal1_single): Likewise.
	(movhi_internal): Likewise.
	(movqi_internal): Likewise.
	(movcc_internal1): Correct mnemonic for stw insn. Set correct "type"
	attribute for load/store instructions.
	(mov<mode>_hardfloat): Set correct "type" attribute for load/store
	instructions.
	(mov<mode>_softfloat): Likewise.
	(mov<mode>_hardfloat32): Likewise.
	(mov<mode>_hardfloat64): Likewise.
	(mov<mode>_softfloat64): Likewise.
	(movdi_internal32): Likewise.
	(movdi_internal64): Likewise.
	(probe_stack_<mode>): Likewise.

2013-03-20  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/vector.md (VEC_R): Add 32-bit integer, binary
	floating point, and decimal floating point to reload iterator.

	* config/rs6000/constraints.md (wl constraint): New constraints to
	return FLOAT_REGS if certain options are used to reduce the number
	of separate patterns that exist in the file.
	(wx constraint): Likewise.
	(wz constraint): Likewise.

	* config/rs6000/rs6000.c (rs6000_debug_reg_global): If
	-mdebug=reg, print wg, wl, wx, and wz constraints.
	(rs6000_init_hard_regno_mode_ok): Initialize new constraints.
	Initialize the reload functions for 64-bit binary/decimal floating
	point types.
	(reg_offset_addressing_ok_p): If we are on a power7 or later, use
	LFIWZX and STFIWX to load/store 32-bit decimal types, and don't
	create the buffer on the stack to overcome not having a 32-bit
	load and store.
	(rs6000_emit_move): Likewise.
	(rs6000_secondary_memory_needed_rtx): Likewise.
	(rs6000_alloc_sdmode_stack_slot): Likewise.
	(rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f
	via xxlxor, just like DFmode 0.0.

	* config/rs6000/rs6000.h (TARGET_NO_SDMODE_STACK): New macro,
	define as 1 if we are running on a power7 or newer.
	(enum r6000_reg_class_enum): Add new constraints.

	* config/rs6000/dfp.md (movsd): Delete, combine with binary
	floating point moves in rs6000.md.  Combine power6x (mfpgpr) moves
	with other moves by using conditional constraits (wg).  Use LFIWZX
	and STFIWX for loading SDmode on power7.  Use xxlxor to create
	0.0f.
	(movsd splitter): Likewise.
	(movsd_hardfloat): Likewise.
	(movsd_softfloat): Likewise.

	* config/rs6000/rs6000.md (FMOVE32): New iterators to combine
	binary and decimal floating point moves.
	(fmove_ok): New attributes to combine binary and decimal floating
	point moves, and to combine power6x (mfpgpr) moves along normal
	floating moves.
	(real_value_to_target): Likewise.
	(f32_lr): Likewise.
	(f32_lm): Likewise.
	(f32_li): Likewise.
	(f32_sr): Likewise.
	(f32_sm): Likewise.
	(f32_si): Likewise.
	(movsf): Combine binary and decimal floating point moves.  Combine
	power6x (mfpgpr) moves with other moves by using conditional
	constraits (wg).  Use LFIWZX and STFIWX for loading SDmode on
	power7.
	(mov<mode> for SFmode/SDmode); Likewise.
	(SFmode/SDmode splitters): Likewise.
	(movsf_hardfloat): Likewise.
	(mov<mode>_hardfloat for SFmode/SDmode): Likewise.
	(movsf_softfloat): Likewise.
	(mov<mode>_softfloat for SFmode/SDmode): Likewise.

	* doc/md.texi (PowerPC and IBM RS6000 constraints): Document wl,
	wx and wz constraints.

	* config/rs6000/constraints.md (wg constraint): New constraint to
	return FLOAT_REGS if -mmfpgpr (power6x) was used.

	* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wg
	constraint.

	* config/rs6000/rs6000.c (rs6000_debug_reg_global): If
	-mdebug=reg, print wg, wl, wx, and wz constraints.
	(rs6000_init_hard_regno_mode_ok): Initialize new constraints.
	Initialize the reload functions for 64-bit binary/decimal floating
	point types.
	(reg_offset_addressing_ok_p): If we are on a power7 or later, use
	LFIWZX and STFIWX to load/store 32-bit decimal types, and don't
	create the buffer on the stack to overcome not having a 32-bit
	load and store.
	(rs6000_emit_move): Likewise.
	(rs6000_secondary_memory_needed_rtx): Likewise.
	(rs6000_alloc_sdmode_stack_slot): Likewise.
	(rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f
	via xxlxor, just like DFmode 0.0.


	* config/rs6000/dfp.md (movdd): Delete, combine with binary
	floating point moves in rs6000.md.  Combine power6x (mfpgpr) moves
	with other moves by using conditional constraits (wg).  Use LFIWZX
	and STFIWX for loading SDmode on power7.
	(movdd splitters): Likewise.
	(movdd_hardfloat32): Likewise.
	(movdd_softfloat32): Likewise.
	(movdd_hardfloat64_mfpgpr): Likewise.
	(movdd_hardfloat64): Likewise.
	(movdd_softfloat64): Likewise.

	* config/rs6000/rs6000.md (FMOVE64): New iterators to combine
	64-bit binary and decimal floating point moves.
	(FMOVE64X): Likewise.
	(movdf): Combine 64-bit binary and decimal floating point moves.
	Combine power6x (mfpgpr) moves with other moves by using
	conditional constraits (wg).
	(mov<mode> for DFmode/DDmode): Likewise.
	(DFmode/DDmode splitters): Likewise.
	(movdf_hardfloat32): Likewise.
	(mov<mode>_hardfloat32 for DFmode/DDmode): Likewise.
	(movdf_softfloat32): Likewise.
	(movdf_hardfloat64_mfpgpr): Likewise.
	(movdf_hardfloat64): Likewise.
	(mov<mode>_hardfloat64 for DFmode/DDmode): Likewise.
	(movdf_softfloat64): Likewise.
	(mov<mode>_softfloat64 for DFmode/DDmode): Likewise.
	(reload_<mode>_load): Move to later in the file so they aren't in
	the middle of the floating point move insns.
	(reload_<mode>_store): Likewise.

	* doc/md.texi (PowerPC and IBM RS6000 constraints): Document wg
	constraint.

	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Print out wg
	constraint if -mdebug=reg.
	(rs6000_initi_hard_regno_mode_ok): Enable wg constraint if
	-mfpgpr.  Enable using dd reload support if needed.

	* config/rs6000/dfp.md (movtd): Delete, combine with 128-bit
	binary and decimal floating point moves in rs6000.md.
	(movtd_internal): Likewise.

	* config/rs6000/rs6000.md (FMOVE128): Combine 128-bit binary and
	decimal floating point moves.
	(movtf): Likewise.
	(movtf_internal): Likewise.
	(mov<mode>_internal, TDmode/TFmode): Likewise.
	(movtf_softfloat): Likewise.
	(mov<mode>_softfloat, TDmode/TFmode): Likewise.

	* config/rs6000/rs6000.md (movdi_mfpgpr): Delete, combine with
	movdi_internal64, using wg constraint for move direct operations.
	(movdi_internal64): Likewise.

	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Print
	MODES_TIEABLE_P for selected modes.  Print the numerical value of
	the various virtual registers. Use GPR/FPR first/last values,
	instead of hard coding the register numbers.  Print which modes
	have reload functions registered.
	(rs6000_option_override_internal): If -mdebug=reg, trace the
	options settings before/after setting cpu, target and subtarget
	settings.
	(rs6000_secondary_reload_trace): Improve the RTL dump for
	-mdebug=addr and for secondary reload failures in
	rs6000_secondary_reload_inner.
	(rs6000_secondary_reload_fail): Likewise.
	(rs6000_secondary_reload_inner): Likewise.

	* config/rs6000/rs6000.md (FIRST_GPR_REGNO): Add convenience
	macros for first/last GPR and FPR registers.
	(LAST_GPR_REGNO): Likewise.
	(FIRST_FPR_REGNO): Likewise.
	(LAST_FPR_REGNO): Likewise.

	* config/rs6000/vector.md (mul<mode>3): Use the combined macro
	VECTOR_UNIT_ALTIVEC_OR_VSX_P instead of separate calls to
	VECTOR_UNIT_ALTIVEC_P and VECTOR_UNIT_VSX_P.
	(vcond<mode><mode>): Likewise.
	(vcondu<mode><mode>): Likewise.
	(vector_gtu<mode>): Likewise.
	(vector_gte<mode>): Likewise.
	(xor<mode>3): Don't allow logical operations on TImode in 32-bit
	to prevent the compiler from converting DImode operations to
	TImode.
	(ior<mode>3): Likewise.
	(and<mode>3): Likewise.
	(one_cmpl<mode>2): Likewise.
	(nor<mode>3): Likewise.
	(andc<mode>3): Likewise.

	* config/rs6000/constraints.md (wt constraint): New constraint
	that returns VSX_REGS if TImode is allowed in VSX registers.

	* config/rs6000/predicates.md (easy_fp_constant): 0.0f is an easy
	constant under VSX.

	* config/rs6000/rs6000-modes.def (PTImode): Define, PTImode is
	similar to TImode, but it is restricted to being in the GPRs.

	* config/rs6000/rs6000.opt (-mvsx-timode): New switch to allow
	TImode to occupy a single VSX register.

	* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Default to
	-mvsx-timode for power7/power8.
	(power7 cpu): Likewise.
	(power8 cpu): Likewise.

	* config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Make
	sure that TFmode/TDmode take up two registers if they are ever
	allowed in the upper VSX registers.
	(rs6000_hard_regno_mode_ok): If -mvsx-timode, allow TImode in VSX
	registers.
	(rs6000_init_hard_regno_mode_ok): Likewise.
	(rs6000_debug_reg_global): Add debugging for PTImode and wt
	constraint.  Print if LRA is turned on.
	(rs6000_option_override_internal): Give an error if -mvsx-timode
	and VSX is not enabled.
	(invalid_e500_subreg): Handle PTImode, restricting it to GPRs.  If
	-mvsx-timode, restrict TImode to reg+reg addressing, and PTImode
	to reg+offset addressing.  Use PTImode when checking offset
	addresses for validity.
	(reg_offset_addressing_ok_p): Likewise.
	(rs6000_legitimate_offset_address_p): Likewise.
	(rs6000_legitimize_address): Likewise.
	(rs6000_legitimize_reload_address): Likewise.
	(rs6000_legitimate_address_p): Likewise.
	(rs6000_eliminate_indexed_memrefs): Likewise.
	(rs6000_emit_move): Likewise.
	(rs6000_secondary_reload): Likewise.
	(rs6000_secondary_reload_inner): Handle PTImode.  Allow 64-bit
	reloads to fpr registers to continue to use reg+offset addressing,
	but 64-bit reloads to altivec registers need reg+reg addressing.
	Drop test for PRE_MODIFY, since VSX loads/stores no longer support
	it.  Treat LO_SUM like a PLUS operation.
	(rs6000_secondary_reload_class): If type is 64-bit, prefer to use
	FLOAT_REGS instead of VSX_RGS to allow use of reg+offset
	addressing.
	(rs6000_cannot_change_mode_class): Do not allow TImode in VSX
	registers to share a register with a smaller sized type, since VSX
	puts scalars in the upper 64-bits.
	(print_operand): Add support for PTImode.
	(rs6000_register_move_cost): Use VECTOR_MEM_VSX_P instead of
	VECTOR_UNIT_VSX_P to catch types that can be loaded in VSX
	registers, but don't have arithmetic support.
	(rs6000_memory_move_cost): Add test for VSX.
	(rs6000_opt_masks): Add -mvsx-timode.

	* config/rs6000/vsx.md (VSm): Change to use 64-bit aligned moves
	for TImode.
	(VSs): Likewise.
	(VSr): Use wt constraint for TImode.
	(VSv): Drop TImode support.
	(vsx_movti): Delete, replace with versions for 32-bit and 64-bit.
	(vsx_movti_64bit): Likewise.
	(vsx_movti_32bit): Likewise.
	(vec_store_<mode>): Use VSX iterator instead of vector iterator.
	(vsx_and<mode>3): Delete use of '?' constraint on inputs, just put
	one '?' on the appropriate output constraint.  Do not allow TImode
	logical operations on 32-bit systems.
	(vsx_ior<mode>3): Likewise.
	(vsx_xor<mode>3): Likewise.
	(vsx_one_cmpl<mode>2): Likewise.
	(vsx_nor<mode>3): Likewise.
	(vsx_andc<mode>3): Likewise.
	(vsx_concat_<mode>): Likewise.
	(vsx_xxpermdi_<mode>): Fix thinko for non V2DF/V2DI modes.

	* config/rs6000/rs6000.h (MASK_VSX_TIMODE): Map from
	OPTION_MASK_VSX_TIMODE.
	(enum rs6000_reg_class_enum): Add RS6000_CONSTRAINT_wt.
	(STACK_SAVEAREA_MODE): Use PTImode instead of TImode.

	* config/rs6000/rs6000.md (INT mode attribute): Add PTImode.
	(TI2 iterator): New iterator for TImode, PTImode.
	(wd mode attribute): Add values for vector types.
	(movti_string): Replace TI move operations with operations for
	TImode and PTImode.  Add support for TImode being allowed in VSX
	registers.
	(mov<mode>_string, TImode/PTImode): Likewise.
	(movti_ppc64): Likewise.
	(mov<mode>_ppc64, TImode/PTImode): Likewise.
	(TI mode splitters): Likewise.

	* doc/md.texi (PowerPC and IBM RS6000 constraints): Document wt
	constraint.

[gcc/testsuite]
2013-03-20  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/mmfpgpr.c: New test.
	* gcc.target/powerpc/sd-vsx.c: Likewise.
	* gcc.target/powerpc/sd-pwr6.c: Likewise.
	* gcc.target/powerpc/vsx-float0.c: Likewise.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196831 138bc75d-0d04-0410-961f-82ee72b054a4
2013-03-20  Martin Jambor  <mjambor@suse.cz>

	* params.def (PARAM_IPA_CP_ARRAY_INDEX_HINT_BONUS): New parameter.
	* ipa-cp.c (hint_time_bonus): Add abonus for known array indices.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196832 138bc75d-0d04-0410-961f-82ee72b054a4
	* config/i386/i386.md (*movti_internal): Set prefix attribute to
	maybe_vex for sselog1 and ssemov types.
	(*movdi_internal): Reorder operand constraints.
	(*movsi_internal): Ditto.  Set prefix attribute to
	maybe_vex for sselog1 and ssemov types.
	(*movtf_internal): Set prefix attribute to maybe_vex
	for sselog1 and ssemov types.
	(*movdf_internal): Ditto.  Set prefix_data16 attribute for
	DImode ssemov types.  Reorder operand constraints.
	(*movsf_internal): Set type of alternatives 3,4 to imov.  Set prefix
	attribute to maybe_vex for sselog1 and ssemov types.  Set prefix_data16
	attribute for SImode ssemov types.  Reorder operand constraints.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196834 138bc75d-0d04-0410-961f-82ee72b054a4
	* config/i386/i386.md (*movoi_internal_avx): Emit insn template
	depending on type attribute.
	(*movti_internal): Ditto.
	(*movtf_internal): Ditto.
	(*movxf_internal): Ditto.
	(*movdf_internal): Ditto.
	(*movsf_internal): Ditto.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196841 138bc75d-0d04-0410-961f-82ee72b054a4
2013-03-20  Robert Mason  <rbmj@verizon.net>

	* config/vxlib-tls.c (__gthread_get_tsd_data,)
	(__gthread_set_tsd_data, __gthread_enter_tsd_dtor_context,)
	(__gthread_leave_tsd_dtor_context): Add prototypes.
	(tls_delete_hook): Update.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196842 138bc75d-0d04-0410-961f-82ee72b054a4
Daily bump.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196847 138bc75d-0d04-0410-961f-82ee72b054a4