Fix write issues to Wishbone interface
[SIM] Add Wishbone write test scenario
Refactor testDMA.cpp, add test for Wishbone attached memory in addition to DDR memory tests.
Fix DDR memory access to support 64,128,256 etc. data payload width
Update TOP files to be more suitable for instantiation:
- remove DDR core generics, correct values are stored in the IP core main file and
it's too hard to manually modify them anyway
- add additional ports to the top entity
- add suitable description in comments
- update Artix version with correct signal routing when instatiating
Update DDR core to v1.9 (ISE 14.6)
- change input clock from differential to no_buffer (for instantiation
  purposes)
Update TOP module for Artix project.
It's now possible to run it directly on AFC card with correct PLL
clocking. Also, update UCF to support newer DDR core version.
Update ISE project file with new DDR core file names.
Switch PCIe testbench to simulate Artix project.
This means also updating DDR model configuration and PCIe Root Port
model checks.
Fix DDR reset scheme & addressing issues for Artix project.
Update Questa makefile & remove redundant wave definitions.