icache: fix invalidate while refill bug

When an invalidate signal would occur at the same time as a
refill is ongoing, the invalidate address would leak out on
ibus, potentially causing a bus error.
immu: line up input/output port declarations

No functional change.
immu: ack all spr accesses to the immu spr group

Any accesses to not implemented sprs would otherwise lock up
the pipeline, since it nowdays expects spr accesses to be acked.
Reads from not implemented sprs return 0, and writes are nops.
dmmu: line up input/output port declarations

No functional change.
dmmu: ack all spr accesses to the immu spr group

Any accesses to not implemented sprs would otherwise lock up
the pipeline, since it nowdays expects spr accesses to be acked.
Reads from not implemented sprs return 0, and writes are nops.