Preserve subregister liveranges in register coalescer.
Tablegen'erate lanemasks for register units

Now we can relate lanemasks in a virtual register to register units.
LiveIntervalUnion: allow specification of liverange when unifying/extracting

This allows it to add subregister ranges into the union.
Respect subregister liveness when allocating registers
Do not add implicit defs/uses when tracking subregister liveness
MachineVerifier: Allow LiveInterval segments to end at a partial write

In the subregister liveness tracking case we do not create implicit
reads on partial register writes anymore, still we need to produce a new
ssa value for partial writes so the live segment has to end.
MachineVerifier: allow physreg use if just a subreg is defined

We can't mark partially undefined registers, so we have to allow reading
a register in the machine verifier if just parts of a register are
defined.
Enable subreg liveness on ARM
Tests: Use CHECK-LABEL where possible
Tests: Be less dependent on a specific schedule/regalloc
Tests: Do not unnecessarily depend on kill comments
Enable MI Sched for x86.
Enable ARM MI Sched.
ARM: use new-style bundles without BUNDLE marker in Thumb2ITBlock