Show stackmap entry encodings in stackmap debug logs. This makes it easier to
cross-reference debug output with encoded stack-maps, and to create stackmap
test-cases. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195874 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Add support for ISD::FROUND

NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195878 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Use SGPR_32 register class for 32-bit SMRD outputs

Writing to the M0 register from an SMRD instruction hangs the GPU, so
we need to use the SGPR_32 register class, which does not include M0.

NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195879 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Implement spilling of SGPRs v5

SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions.

v2:
  - Fix encoding of Lane Mask
  - Use correct register flags, so we don't overwrite the low dword
    when restoring multi-dword registers.

v3:
  - Register spilling seems to hang the GPU, so replace all shaders
    that need spilling with a dummy shader.

v4:
  - Fix *LANE definitions
  - Change destination reg class for 32-bit SMRD instructions

v5:
  - Remove small optimization that was crashing Serious Sam 3.

https://bugs.freedesktop.org/show_bug.cgi?id=68224
https://bugs.freedesktop.org/show_bug.cgi?id=71285

NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195880 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Expand vector FABS

NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195881 91177308-0d34-0410-b5e6-96231b3b80d8
The R600 has its own asm printer which doesn't use GlobalPrefix. Drop it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195883 91177308-0d34-0410-b5e6-96231b3b80d8
Don't set GlobalPrefix to the default value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195884 91177308-0d34-0410-b5e6-96231b3b80d8
Add IIC_ prefix to PPC instruction-class names

This adds the IIC_ prefix to the instruction itinerary class names, giving the
PPC backend a naming convention for itinerary classes that is more consistent
with that used by the X86 and ARM backends.

Instruction scheduling in the PPC backend needs a bunch of cleanup and
improvement (especially for the ooo cores). This is just a preliminary step.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195890 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Implement the following optimizations using dominance information to
make PIC calls a little more efficient:

1. Remove instructions setting up $gp if it is known that a function has been
   called at least once.
2. Save the address of a called function in a register instead of loading
   it from the GOT at every call site.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195892 91177308-0d34-0410-b5e6-96231b3b80d8
Add MipsOptimizePICCall.cpp to CMakeLists.txt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195894 91177308-0d34-0410-b5e6-96231b3b80d8
DebugInfo: Do not include variables only referenced by templates in aranges.

ARanges included even extern variables referenced by pointer non-type
template parameters even though that variable isn't part of this
compilation unit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195895 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Redefine TAILCALL as a pseudo instruction.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195896 91177308-0d34-0410-b5e6-96231b3b80d8
Check in conditional branches for constant islands. Still need to finish
conditional branches for very large targets. That will be the next small
patch. Everything now should in principle work as good (functionality
wise) as without constant islands so we decided at Mips/Imagination to
make constant islands the default for Mips16 now so that it will get
excercised a lot and this port is still experimentatl though hopefully soon
we will change the status. Some more cleanup and code review is in order
but things are converging fast.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195902 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: Fix a bug about disassembling post-index load single element to 4 vectors


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195903 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the variable only used by assert to avoid the build failure
caused by build options [-Werror,-Wunused-variable].


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195905 91177308-0d34-0410-b5e6-96231b3b80d8