i965: Zero out {point_sprite,flat}_enables in calculate_attr_overrides.

calculate_attr_overrides is responsible for computing the point sprite
and flat-shading enable bitfields.  It does so by OR'ing in a bunch of
bits.  However, it relied on the caller to set the initial value to
zero.  This is pretty fragile - if the caller neglects to zero out those
variables, then the enable bitfields end up full of garbage, which shows
up as random things being flat-shaded.

This patch moves the zero-initialization into calculate_attr_overrides,
so that the computation is completely in one place.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Paul Berry <stereotype441@gmail.com>
i965: Use {point_sprite,flat}_enable variable names instead of dw*.

Calling the local variables flat_enable and point_sprite_enable is
clearer than dw16 and such.  It also matches the names used in
calculate_attr_overrides, which computes them.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Paul Berry <stereotype441@gmail.com>
i965: Add BRW_REGISTER_TYPE_DF.

We don't use double floats yet, but the new Gen8 disassembler will
support them.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Add #defines for new Broadwell math functions.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Add SFID #defines for media stuff.

While we probably won't ever use these, having them makes it easy to
share disassembler code between intel-gpu-tools and Mesa.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Add a new representation for Broadwell shader instructions.

Broadwell significantly changes the EU instruction encoding.  Many of
the fields got moved to different bit positions; some even got split
in two.

With so many changes, it was infeasible to continue using struct
brw_instruction.  We needed a new representation.

This new approach is a bit different: rather than a struct, I created a
class that has four DWords, and helper functions that read/write various
bits.  This has several advantages:

1. We can create several different names for the same bits.  For
   example, conditional modifiers, SFID for SEND instructions, and the
   MATH instruction's function opcode are all stored in bits 27:24.

   In each situation, we can use the appropriate setter function:
   set_sfid(), set_math_function(), or set_cond_modifier().  This
   is much easier to follow.

2. Since the fields are expressed using the original 128-bit numbers,
   the code to create the getter/setter functions follows the table in
   the documentation very closely.

To aid in debugging, I've enabled -fkeep-inline-functions when building
gen8_instruction.c.  Otherwise, these functions cannot be called by
gdb, making it insanely difficult to print out anything.

Kenneth Graunke wrote most of this code.  Damien Lespiau ported it to
C99.  Xiang Haihao added media fields.  Zhao Yakui added indirect
addressing support.  Eric Anholt added an assertion to make sure that
values fit in the alloted number of bits.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
i965: Implement a disassembler for Broadwell's new instruction encoding

Heavily based on Keith Packard's existing brw_disasm.c code.  I've tried
to go through most of the pieces (like SFIDs) and update the lists to
include features added in recent generations.

I had to use C++ since my new instruction representation requires it.
Unfortunately, C++98 doesn't allow the use of C99 array initializers,
which makes the arrays mapping values to strings harder to read.  I
tried to compensate for this failing by adding additional comments.

The disassembly can definitely be improved, but this should at least
get INTEL_DEBUG=vs/fs working.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Add a new infrastructure for generating Broadwell shader assembly.

This replaces the brw_eu_emit.c layer for Broadwell.  It will be
used by both the vector and scalar shader backends.

v2: Port to use the C-based instruction representation.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Create a new vec4 backend for Broadwell.

This replaces the old vec4_generator backend.

v2: Port to use the C-based instruction representation.  Also, remove
    Geometry Shader offset hacks - the visitor will handle those instead
    of this code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Create a new fragment shader backend for Broadwell.

This replaces the old fs_generator backend.

v2: Port to the C-based representation of assembly instructions.
    Fix texturing after the texture-grf merge.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Reserve space for "Vertex Count" in GS outputs.

v2: Also increment ir->offset in the GS visitor, rather than at the
    final assembly generation stage (requested by Paul).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Duplicate gen7_atoms to gen8_atoms.

It's going to diverge significantly.  Starting out with a copy allows
future patches to change atoms one by one.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Use the Sandybridge VUE format on Broadwell as well.

It hasn't changed.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
i965: Bump generation assertions on workaround flushes.

These workaround flushes may not be necessary on Gen8.  Investigation is
needed.  Tentatively, let's do them out of caution.

v2: [chadv]
  - Comment that flush may not be needed.
  - Make assertion conditions symmetrical.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
i965: Introduce an OUT_RELOC64 macro.

Broadwell uses 48-bit addresses.  The first DWord is the low 32 bits,
and the second DWord is the high 16 bits.

Since individual buffers shouldn't be larger than 4GB in size, any
offsets into those buffers (buffer->offset + delta) should fit in the
low 32 bits.  So I believe we can simply emit 0 for the high 16-bits,
and drm_intel_bo_emit_reloc() should patch it up.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Update SF, SBE, and RASTER state for Broadwell.

The attribute override portion of 3DSTATE_SBE was split out into
3DSTATE_SBE_SWIZ; various bits of 3DSTATE_SF were split out into
3DSTATE_RASTER.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Replace DEPTH_STENCIL_STATE with Gen8's 3DSTATE_WM_DEPTH_STENCIL.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Add the new 3DSTATE_PS_BLEND state packet.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Rework 3DSTATE_VS for Broadwell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>