made data cache single port.
cache port is occupied for cache access latency.
fixed a issue in cacheController.cpp in modeling write latency.
missed write latency is half of hit write latency
starting unifying code
swapping data cache part and other in get_port
finished a template code
fixed bugs and minor changes
fixed bugs and warnings
minimized code changes
fixed a bug in get_port
resolved the conflicts
fixed bugs
updated after merge
updated after merge
fixed bugs
updated after merge