Tweak for code style
Upgrade the pipeline to use a new internal state system

 - Fetch now emits a map {:icode Icode :pc Int}
 - Decode now has a :pc key in the emitted map
 - register->val now provides the correct pc+4 behavior when reading the PC
 - Execute now generates a map {:dst, :addr, :val} map
 - All stages now have sane no-op default values for this representation
Fix typos in SAL
Move common byte/icode ops into isa

 - Refactor for newline style
 - Rewrite register->val to be common across processor impl's
 - Bring in the upgrade-writeback-command
 - Add a opcode->fn mapping which is spec complete
 - Add a bytecode->opcode mapping which is spec complete
Typo in the bytecode->opcode map
Drop core.typed from isa
HUGE codebase restructure

This commit totally breaks stuff. But it also lays the groundwork for
making the processors bytecode vs. vector code agnostic rather than
requiring separate decode implementations to deal with decoding vectors
vs bytecodes.

Added opcode normalization to make dealing with the various corner cases
of keyword parameters vs integer codes disappear.

Restructured a bunch of the code that was pulled out to make the
namespaces make more sense.

At least one refactor for style in here too.