gallivm: Fix build with LLVM 3.3

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
radeon: Fix build with LLVM 3.3

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
r600g/compute: Fix build error in debug code

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
r600g: Don't set the dest cache bits on surface sync for R600_CONTEXT_FLUSH_AND_INV

We are already emitting a EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT packet
when this flush flag is set, so flushing the dest caches with a
SURFACE_SYNC should not be necessary.

The motivation for this change is that emitting a SURFACE_SYNC packet with
the CB bits set was causing compute shaders to hang on Cayman.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
i965: Fix SNB GPU hangs when a blorp batch is the first thing to execute.

The GPU apparently goes looking for constants even though there are no
shader stages enabled, and gets stuck because we haven't told it there are
no constants to collect.  If any other user of the 3D pipeline had run
(even the Render accel of the X server!) since power on, then the in-GPU
constant buffers would have been set up with some contents we didn't use,
and we would succeed.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56416
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Dave Airlie <airlied@redhat.com>
NOTE: This is a candidate for the stable branches.
tgsi: allow negation of all integer types

It's valid because we reuse certain arithmetic operations
for both signed and unsigned types (e.g. uadd, umad, which
have a bit unfortunate naming)

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
draw/gs: don't crash when vs/gs signatures don't match

instead of crashing just fill zeros at the input slots that don't
match, that's the mandated behavior and it avoids debug asserts.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
wayland: Make eglQueryBufferWL succeed for width and height requests too

Following the addition of the EGL_WIDTH and EGL_HEIGHT this function should
return EGL_TRUE for those requested attributes too.
i965/vs: Do round-robin register allocation on gen6+ like we do in the FS.

This will free instruction scheduling to make better choices.  No
statistically significant performance difference on GLB2.7 (n=93).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Make dump_instructions be a virtual method of the visitor.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Share the register file enum between the two backends.

I need this so I can look at vec4 and fs registers' files from the same
.cpp file without namespaces.  As far as I can tell we never rely on the
particular numerical values of the files, though I thought it sounded like
a good idea when doing the VS (it turns out having 0 be BAD_FILE is nicer).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Move FS instruction scheduling to a non-FS-specific file.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Pull a couple of FS scheduling functions out to methods.

These will get virtualized as we add VS scheduling support.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Move most of the FS instruction scheduler code to a general class.

About half of this is shareable with the VS code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965/vs: Add instruction scheduling.

While this is ignorant of dependency control, it's still good for a 0.39%
+/- 0.08% performance improvement on GLBenchmark 2.7 (n=548)

v2: Rewrite as a subclass of the base class for the FS instruction
    scheduler, inheriting the same latency information.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
util/prim: fix primitive trimming for triangles with adjacency

Fix for PIPE_PRIM_TRIANGLES_ADJACENCY and PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>
util/prim: clean up and add comments

Move together (or add) functions to decompose/reduce/assemble a primitive,
give them consistent names, and document them.  Add u_prim_vertex_count() so
that the vertex count information can be used elsewhere.

u_assembled_primitive() will be removed in a folow-on commit.

[olv: fix a warning when -Wold-style-declaration is enabled]

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>
draw: use u_assembled_prim() instead of u_assembled_primitive()

The latter function is also removed as a result of the change.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>
util/prim: fix the name of the include guard

It should be U_PRIM_H, not U_BLIT_H.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>
util/prim: use vertex count info in u_validate_pipe_prim()

As a side effect, primitives with adjacency are now correctly validated.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>