gcc/

	* gimple-ssa-strength-reduction.c: Include tree-affine.h.
	(name_expansions): New static variable.
	(alt_base_map): Ditto.
	(get_alternative_base): New function.
	(find_basis_for_candidate): For CAND_REF, optionally call
	find_basis_for_base_expr with the returned value from
	get_alternative_base.
	(record_potential_basis): Add new parameter 'base' of type 'tree';
	add an assertion of non-NULL base; use base to set node->base_expr.
	(alloc_cand_and_find_basis): Update; call record_potential_basis
	for CAND_REF with the returned value from get_alternative_base.
	(replace_refs): Dump details on the replacing.
	(execute_strength_reduction): Call pointer_map_create for
	alt_base_map; call free_affine_expand_cache with &name_expansions.

gcc/testsuite/

	* gcc.dg/tree-ssa/slsr-39.c: Update.
	* gcc.dg/tree-ssa/slsr-41.c: New test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205655 138bc75d-0d04-0410-961f-82ee72b054a4
	PR tree-optimization/59355
	* ipa-devirt.c (gate_ipa_devirt): Return false if
	!flag_devirtualize.
	* opts.c (common_handle_option): Fix comment spelling.

	* g++.dg/ipa/pr59355.C: New test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205656 138bc75d-0d04-0410-961f-82ee72b054a4
include/
	* longlong.h: New file.

libgcc/
	* longlong.h: Delete (moved to include/).

libquadmath/
	* Makefile.am (AM_CPPFLAGS): Define.
	* Makefile.in: Regenerate.
	* printf/gmp-impl.h: Remove path from longlong.h include.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205659 138bc75d-0d04-0410-961f-82ee72b054a4
	PR target/59163
	* config/i386/i386.c (ix86_legitimate_combined_insn): If for
	!TARGET_AVX there is misaligned MEM operand with vector mode
	and get_attr_ssememalign is 0, return false.
	(ix86_expand_special_args_builtin): Add get_pointer_alignment
	computed alignment and for non-temporal loads/stores also
	at least GET_MODE_ALIGNMENT as MEM_ALIGN.
	* config/i386/sse.md
	(<sse>_loadu<ssemodesuffix><avxsizesuffix><mask_name>,
	<sse>_storeu<ssemodesuffix><avxsizesuffix>,
	<sse2_avx_avx512f>_loaddqu<mode><mask_name>,
	<sse2_avx_avx512f>_storedqu<mode>, <sse3>_lddqu<avxsizesuffix>,
	sse_vmrcpv4sf2, sse_vmrsqrtv4sf2, sse2_cvtdq2pd, sse_movhlps,
	sse_movlhps, sse_storehps, sse_loadhps, sse_loadlps,
	*vec_interleave_highv2df, *vec_interleave_lowv2df,
	*vec_extractv2df_1_sse, sse2_movsd, sse4_1_<code>v8qiv8hi2,
	sse4_1_<code>v4qiv4si2, sse4_1_<code>v4hiv4si2,
	sse4_1_<code>v2qiv2di2, sse4_1_<code>v2hiv2di2,
	sse4_1_<code>v2siv2di2, sse4_2_pcmpestr, *sse4_2_pcmpestr_unaligned,
	sse4_2_pcmpestri, sse4_2_pcmpestrm, sse4_2_pcmpestr_cconly,
	sse4_2_pcmpistr, *sse4_2_pcmpistr_unaligned, sse4_2_pcmpistri,
	sse4_2_pcmpistrm, sse4_2_pcmpistr_cconly): Add ssememalign attribute.
	* config/i386/i386.md (ssememalign): New define_attr.

	* g++.dg/torture/pr59163.C: New test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205661 138bc75d-0d04-0410-961f-82ee72b054a4
	* gcc-interface/trans.c (Case_Statement_to_gnu): Do not push a binding
	level for each branch if this is a case expression in Ada 2012.
	(gnat_to_gnu) <case N_Expression_With_Actions>: Adjust comment.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205662 138bc75d-0d04-0410-961f-82ee72b054a4
	PR target/59163
	* config/i386/i386.c (ix86_legitimate_combined_insn): If for
	!TARGET_AVX there is misaligned MEM operand with vector mode
	and get_attr_ssememalign is 0, return false.
	(ix86_expand_special_args_builtin): Add get_pointer_alignment
	computed alignment and for non-temporal loads/stores also
	at least GET_MODE_ALIGNMENT as MEM_ALIGN.
	* config/i386/sse.md
	(<sse>_loadu<ssemodesuffix><avxsizesuffix><mask_name>,
	<sse>_storeu<ssemodesuffix><avxsizesuffix>,
	<sse2_avx_avx512f>_loaddqu<mode><mask_name>,
	<sse2_avx_avx512f>_storedqu<mode>, <sse3>_lddqu<avxsizesuffix>,
	sse_vmrcpv4sf2, sse_vmrsqrtv4sf2, sse2_cvtdq2pd, sse_movhlps,
	sse_movlhps, sse_storehps, sse_loadhps, sse_loadlps,
	*vec_interleave_highv2df, *vec_interleave_lowv2df,
	*vec_extractv2df_1_sse, sse2_movsd, sse4_1_<code>v8qiv8hi2,
	sse4_1_<code>v4qiv4si2, sse4_1_<code>v4hiv4si2,
	sse4_1_<code>v2qiv2di2, sse4_1_<code>v2hiv2di2,
	sse4_1_<code>v2siv2di2, sse4_2_pcmpestr, *sse4_2_pcmpestr_unaligned,
	sse4_2_pcmpestri, sse4_2_pcmpestrm, sse4_2_pcmpestr_cconly,
	sse4_2_pcmpistr, *sse4_2_pcmpistr_unaligned, sse4_2_pcmpistri,
	sse4_2_pcmpistrm, sse4_2_pcmpistr_cconly): Add ssememalign attribute.
	* config/i386/i386.md (ssememalign): New define_attr.

	* g++.dg/torture/pr59163.C: New test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205663 138bc75d-0d04-0410-961f-82ee72b054a4
	PR rtl-optimization/58726
	* combine.c (force_to_mode): Fix comment typo.  Don't destructively
	modify x for ROTATE, ROTATERT and IF_THEN_ELSE.

	* gcc.c-torture/execute/pr58726.c: New test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205664 138bc75d-0d04-0410-961f-82ee72b054a4
	* gcc-interface/decl.c (components_to_record): Add specific handling
	for fields with zero size and no representation clause.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205665 138bc75d-0d04-0410-961f-82ee72b054a4
2013-12-04  Kugan Vivekanandarajah  <kuganv@linaro.org>

	* config/arm/bpapi-lib.h (TARGET_HAS_NO_HW_DIVIDE): Define for
	architectures that do not have hardware divide instruction.
	i.e. architectures that do not define __ARM_ARCH_EXT_IDIV__.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205666 138bc75d-0d04-0410-961f-82ee72b054a4