Factor MI-Sched in preparation for post-ra scheduling support.

Factor the MachineFunctionPass into MachineSchedulerBase.

Split the DAG class into ScheduleDAGMI and SchedulerDAGMILive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198119 91177308-0d34-0410-b5e6-96231b3b80d8
Stub out a PostMachineScheduler pass.

Placeholder and boilerplate for a PostRA MachineScheduler pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198120 91177308-0d34-0410-b5e6-96231b3b80d8
Move the PostRA scheduler's fixupKills function for reuse.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198121 91177308-0d34-0410-b5e6-96231b3b80d8
Add a PostMachineScheduler pass with generic implementation.

PostGenericScheduler uses either the new machine model or the hazard
checker for top-down scheduling. Most of the infrastructure for PreRA
machine scheduling is reused.

With a some tuning, this should allow MachineScheduler to be default
for all ARM targets, including cortex-A9, using the new machine
model. Likewise, with additional tuning, it should be able to replace
PostRAScheduler for all targets.

The PostMachineScheduler pass does not currently run the
AntiDepBreaker. There is less need for it on targets that are already
running preRA MachineScheduler. I want to prove it's necessary before
committing to the maintenance burden.

The PostMachineScheduler also currently removes kill flags and adds
them all back later. This is a bit ridiculous. I'd prefer passes to
directly use a liveness utility than rely on flags.

A test case that enables this scheduler will be included in a
subsequent checkin that updates the A9 model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198122 91177308-0d34-0410-b5e6-96231b3b80d8
The Cortex-A9 machine model is incomplete. Mark it as such.

Many vector operations never had itineraries. Since the new machine
model was a mapping from existing itinerary classes, we don't have a
model for these. We still want to migrate A9 even though no one has
invested in a complete model, so mark it incomplete to avoid the
scheduler asserting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198123 91177308-0d34-0410-b5e6-96231b3b80d8
Added debugging options: -misched-only-func/block

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198124 91177308-0d34-0410-b5e6-96231b3b80d8
New machine model for cortex-a9. Schedule for resources and latency.

Schedule more conservatively to account for stalls on floating point
resources and latency. Use the AGU resource to model latency stalls
since it's shared between FP and LD/ST instructions. This might not be
completely accurate but should work well in practice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198125 91177308-0d34-0410-b5e6-96231b3b80d8
Uninitialized variable (in never taken path) after factoring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198131 91177308-0d34-0410-b5e6-96231b3b80d8
ARM IAS: handle errors more appropriately

Directive parsers must return false if the target assembler is interested in
handling the directive.  The Error member function returns true always.  Using
the 'return Error()' pattern would incorrectly indicate to the general parser
that the target was not interested in the directive, when in reality it simply
encountered a badly formed directive or some other error.  This corrects the
behaviour to ensure that the parser behaves appropriately.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198132 91177308-0d34-0410-b5e6-96231b3b80d8
CodeGen: silence a C++11 feature warning

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198133 91177308-0d34-0410-b5e6-96231b3b80d8