mcelog: Identify Ivy Bridge properly

Uniquely identify Ivy Bridge even though the machine checks are the same
for Sandy Bridge and Ivy Bridge.  This makes the output for the processor
display "Ivy Bridge".

Signed-off-by: Prarit Bhargava <prarit@redhat.com>
Cc: tony.luck@intel.com
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Merge branch 'master' of ssh://github.com/andikleen/mcelog
mcelog: Decode MISC register when IO MCA occurs

Processors can be configured to report uncorrected PCI Express errors
using machine check.  This is indicated by the MISCV bit being set
in MCi_STATUS together with a specific 0x0E0B MCACOD signature.
In this case the MCi_MISC register contains the PCI Express segment
number and PCI Express requestor ID of the root complex reporting
the error.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>