Loosen the signal pattern for the 20ns constaint; it was too tight.
Take the pll decay parameter back out of the spi.
Upgrade the pll report a bit.
Drop a few bits off the bottom of error.
Too big for b.n, we need b.w.
Adjust the software for the changed register widths.
Simplify the register read functions.
Further trim the pll registers.
Update for the new register widths.  Correct some of the arithmetic.
Extend the range of the pll decay up to 11.
Round instead of truncate the products.
Round in a few more places.  Seems to improve stability a little.
Lower the target multiplier gain for the PLL.
Rework and sanitize the bitshift and register-size calculations.
Fix for current gain target.
Split the constant defs for error and level.
Narrow error_width and level_width a bit more.
Update software for current parameters.
Rework the comments to remove full_width.