chisel: Start integration of Chisel UART.
Merge branch 'master' into uart

Conflicts:
	chisel/src/io/uart.scala
chiselio: UART now seems to work in Verilog simulation.
chisel: Small cleanups, remove random generation of enable signals.
chisel: Enable UART output in emulator again.
chisel: Adapt bemicro project for Chisel UART.
bootloader: Fix horrible typo.