ARC: [plat-eznps] Add eznps platform

This platform include boards:
	Hardware Emulator (HE) version 0,1...
	Simulator based upon nSIM.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: [plat-eznps] Add eznps default board configurations

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: [plat-eznps] ADD eznps DTS file
Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: TLB flush for SMP

This is for cases we need to flush tlb's in several CPU's since a memory
structure may be held by several threads in the same time in different
CPU's.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: ASID with SMP

Each CPU got its own TLB and therefore it's own software cache.
Also each mmu context may reside at the same in several CPU's thanks to
threads sharing the context therefore may have different ASID.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: Add initrd from external file.

We now can easly get rootfs from external file.
It may be cpio, ext2, cramfs...

This makes vmlinux usable not only for internal cpio.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: Handle un-aligned user space access in BE.

Adding endian awarness to un-aligned access exception handling.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: uImage compression mode

It is possible to add configuration for gzip compression.

The default is none, no compression at all.

Signed-off-by: Noam Camus <noamc@ezchip.com>
Changed linux version to EXTRAVERSION = .EZchip_1.0
ARC: [plat-eznps] Add device for cmem
Add new device /dev/cmem.
This device enable access to cmem in other cores.

It is usefull for debugging when gdbserver is attached to process
which runs in a different CPU than gdbserver.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: add gutter above stack top.

reserve space inside task size just above stack top.
Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: copy_to_user_page be SMP aware
When using ptrace there is need to flush icache when application
is on different CPU than gdbserver.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: STAR 9000597649 workaround
When doing TLB flush simulator (nSIM)
trigger flush of internal cache designed for optimization.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: fix cpu idefntifier
Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: Change parse_early_param location

We need it to be after init_early since we set clock there.
It will be used later when evaluating console=...
e.g. in 8250_early.c at BASE_BAUD

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: fix typo with clock speed
Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: handle IPI like TIMER0

Use same irq-generic methods in both cases
Signed-off-by: Noam Camus <noamc@ezchip.com>