sockit: add access to "fpga ddr3" from hps in qsys
cores: add diila - Device Independent Integrated Logic Analyzer core
sockit: add diila debugging of fpga ddr3 avalon signals
cores: add wishbone to avalon bridge core

Core for bridging between wishbone and avalon busses.
Initially only wishbone master to avalon conversion,
and bursting is not yet supported.
cores/mor1kx: use 'version' instead of deprecated 'branch' option

When the the version option was introduced the branch option is
no longer recognised and will be ignored. Even though there is
a fallback to master when there is no version option stated,
explicitly stating it makes it more clear for users what to modify
to get a certain version.
sockit/qsys: remove some redundant reset connections
sockit: use wb_to_avalon_bridge to hook up DDR3 memories
sockit: fix typos in or1200 instantiation
sockit: complete support for or1200