Trace Based Simulation tracks throttle cycles.

Previously, TBS throttled the access stream to make sure that too
many accesses didn't go out to the hybrid memory at once. This update
tracks throttle cycles separately from cycles actually stepping through
the trace.  This prevents the issuing code from having accesses "bunch
up" and all go out at once when long stalls when events like NAND flash
accesses occur.  For example, if an access was issued every 100 cycles
in a trace and a miss causes an access to take 10000 cycles, then when
the miss returns, 100 accesses are immediately ready for issue. This
update prevents that from happening and the accesses are correctly
issued at 100 cycle intervals after the miss completes. This is more
accurate because it simulates how long the CPU would take to process
the instructions necessary to generate the memory trace (assuming the
trace was originally generated from MARSS or another mechanism modeling
a CPU). The goal of this update is to allow TBS experiments to better
estimate IPC based on a smaller number of MARSS runs. For example, we
would like to be able to run a MARSS DRAM-only run and collect the trace
and IPC. Then we could change the hybrid memory configuration and run the
trace to get a new cycle count.  The IPC could then be caused as follows:
IPC_run2 = IPC_run1 * (cycles_run2 / cycles_run1).  The error of this IPC
estimation method is an area that will be investigated in the near future.