Fixing an error in Timer1 setup for __AVR_ATtinyX5__.

In CTC mode on attinyx5, the Counter register is reset on match with OCR1C, not OCR1A.

As a result, the existing code counted 256 time too slow, b/c by default
OCR1C is set to 0xFF, so the count would continue until it overflows.

In other words, we wanted: 1 / (8000000 / 128 / 5) = 80us
But what we got was: 1 / (8000000 / 128 / 256) = 4ms

This fix addresses the problem and ensures that the ISR is called every 80us.

Tested on attiny85.
Fixing an unintended side-effect. I was accidentally turning off other Output Compare Interrupts.
Merge pull request #4 from vace117/master

Fixing Timer1 setup for attiny85