Add Mux1H support for zipped Seq[(Bool, T)]
Fork off some Vec functionality into VecLike

This allows other containers to be more... Vec-like.
Add orderedWrites flag to Mem; make Mem VecLike

Mem(gen, n, orderedWrites = true) supports the normal when() order on Mem
writes.  This has basically the same behavior as Vec.fill(n)(Reg(gen)), except
it compiles and simulates faster.

By default, i.e. orderedWrites = false, multiple writes to the same address
result in undefined behavior.