llvm-tblgen: Mangle operand replacements into the strings in printAliasInstr.

Cuts down the bloat in the AArch64 asm writer a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190527 91177308-0d34-0410-b5e6-96231b3b80d8
Give internal classes hidden visibility.

Worth 100k on a linux/x86_64 Release+Asserts clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190534 91177308-0d34-0410-b5e6-96231b3b80d8
[lit] Add support for attach arbitrary metrics to test results.

 - This is a work-in-progress and all details are subject to change, but I am
   trying to build up support for allowing lit to be used as a driver for
   performance tests (or other tests which might want to record information
   beyond simple PASS/FAIL).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190535 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "Give internal classes hidden visibility."

It works with clang, but GCC has different rules so we can't make all of those
hidden. This reverts commit r190534.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190536 91177308-0d34-0410-b5e6-96231b3b80d8
Debug Info: move class definition of DIRef.

Definition of DIRef used to require the full definition of DIType because
of usage of DIType::isType in DIRef::resolve. We now use DIDescriptor::isType
instead to remove the requirement and move definition of DIRef before DIType.

With this, we can move the definition of DIType::getContext to the header
file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190540 91177308-0d34-0410-b5e6-96231b3b80d8
Try to fix the atom buildbots by adding an explicit 'cpu' to the 'llc' command.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190541 91177308-0d34-0410-b5e6-96231b3b80d8
Add getUnrollingPreferences to TTI

Allow targets to customize the default behavior of the generic loop unrolling
transformation. This will be used by the PowerPC backend when targeting the A2
core (which is in-order with a deep pipeline), and using more aggressive
defaults is important.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190542 91177308-0d34-0410-b5e6-96231b3b80d8
Debug info: add more comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190544 91177308-0d34-0410-b5e6-96231b3b80d8
Move into an anonymous namespace and closer to where it's used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190547 91177308-0d34-0410-b5e6-96231b3b80d8
Implement TTI getUnrollingPreferences for PowerPC

The PowerPC A2 core greatly benefits from aggressive concatenation unrolling;
use the new getUnrollingPreferences to enable this by default when targeting
the PPC A2 core.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190549 91177308-0d34-0410-b5e6-96231b3b80d8
Use the appropriate return type for the compact unwind encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190551 91177308-0d34-0410-b5e6-96231b3b80d8
Fix anachronism/typo in syntax of declaration of llvm.va_start.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190552 91177308-0d34-0410-b5e6-96231b3b80d8
[CMake] Update GetSVN.cmake to use LLVM version control helper scripts.

This allows the logic to work with Git, and also uses the variable names
to match what Clang is actually looking for.

This changes the interface of GetSVN.cmake. Clang change to follow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190556 91177308-0d34-0410-b5e6-96231b3b80d8
Enable MI scheduling (and CodeGen AA) by default for embedded PPC cores

For embedded PPC cores (especially the A2 core), using the MI scheduler with AA
is far superior to the other scheduling options.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190558 91177308-0d34-0410-b5e6-96231b3b80d8
Greatly simplify the PPC A2 scheduling itinerary

As Andy pointed out to me a long time ago, there are no structural hazards in
the later pipeline stages of the A2, and so modeling them is useless. Also,
modeling the top pre-dispatch stages is deceiving because, when multiple
hardware threads are active, those resources are shared among the threads. The
bypass definitions were mostly wrong, and so those have been removed. The
resulting itinerary is much simpler, and more accurate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190562 91177308-0d34-0410-b5e6-96231b3b80d8
Remove pointless assertion after r190376

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190565 91177308-0d34-0410-b5e6-96231b3b80d8
Fix comment to match what the assert actually enforces

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190566 91177308-0d34-0410-b5e6-96231b3b80d8
Move variable under condition where it is used

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190567 91177308-0d34-0410-b5e6-96231b3b80d8
Typo fixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190569 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Don't use trans slot for instructions that read LDS source registers

This fixes some regressions in the piglit local memory store tests
introduced by recent commits which made the scheduler aware of the trans
slot.

It's not possible to test this using lit, because there is no way to
determine from the assembly dumps whether or not an instruction is in
the trans slot.

Even if this were possible, the test would be highly sensitive to
changes in the scheduler and might generate confusing false negatives.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190574 91177308-0d34-0410-b5e6-96231b3b80d8