Changes for r-vex core.

Changed the way mask and input data is latched in cache.
Added AHB master interface to cache.
LRU State changes fixed.

State changes for LRU fixed.
Inidividual flush signal for each way.

Added ability to flush each way individually.
Dynamic enabling/disabling of cache ways.

Added reconfiguration mechanism to dynamically enable/disable
individual ways of cache.
Perf events added. Error/Retry/Split handling in AHB.

Added data cache access and miss event signals to dache out
interface to be used for performance counters. Modified
AHB master to handle error/retry/split responses from slave.
Fixed bugs in reconfiguration mechanism.

The dynamic enabling/disabling of ways should happen when the
data cache is idle. This has been fixed now and tested with
three ERA benchmarks: dft, x264 and matrix multiplication.
Fixed combinatorial loop.
Modified miss events.

Separated the dcache access and miss events into read and write
events. Modified Write-through and Write-back cache controller
logic to make it cleaner and conform to 2-process method.
Fixed critical paths.

Fixed critical paths in Arbiter and Data cache. The cache still
has a critical path in Data cache from Tag RAM to processor stall
signal.
Added CPU generics to cache.

Added CPU generic to cache entity.