FPGA: Compiler directives for using of external RAM and SERDES was added.
FPGA: Spartan6 ICAP was added. Compiler directive for using of Spartan6 ICAP is "SPARTAN6".
FPGA: Interface for a LMS chip was added.

Compiler directive for using of LMS chip is "NO_LMS".
FPGA: Frontend to LMS602D has been redesigned. Second LMS602D was added.
FPGA: User constraints file for xc6slx75 in package fgg484 was added.
FPGA: Width of signal dat_o was changed for implementation on Spartan 6
FPGA: Generation of clock signal for ICAP module was changed for implementation on Spartan 6
FPGA: Generation of clock signal for UmTRX was added (compiler directive UMTRX)
FPGA: Added a Makefile to build UmTRX project
FPGA: Pll cores was added to makefile
FPGA: Precompiled bootloader for UmTRX board was added
FPGA: Fixed link to the ucf file for UMTRX board.
FPGA: Top file for UmTRX project was added
FPGA: .ucf file for UmTRX project was renamed and his structure was optimized
FPGA: Corrected links on top and .ucf files in Makefile for UmTRX project
FPGA: Nets TXD1 and RXD1 was swapped due to fix Issue 7 in UmTRX project
FPGA: Some blocks were switched off and some input and output nets was deleted, because they are unused in project
FPGA: SPI bus were aligned with the project
FPGA: Direction of the SPI lines to the chip has been fixed
FPGA: LMS RESET signal is set to 1 to enable LMS chip after FPGA load.

This should be fine for our testing purposes. Later we may need to do it properly